From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by sourceware.org (Postfix) with ESMTPS id 111FA3858C2C for ; Wed, 20 Dec 2023 09:49:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 111FA3858C2C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 111FA3858C2C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::22e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703065743; cv=none; b=QD8WqiYTzsGvLmSeb31ZaJZfH1160ts/M2cwDuZ6Fvnjke331gRuWeiY8GpwWkPhnmZUyOjXXI5XQG8E7fnZe3mUBi5NLdAA3gGqfmlA09fLvSZg5SMi5EnJH082xRNdDOjx8DstrobZEyIrbdWRjUq6A0RovFi84W2oWcCweoo= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703065743; c=relaxed/simple; bh=e6SkY8/Dtq92NgfctMS/p8/5FEQNtEEYGamNgi2mbgw=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=x45G/hzCl9A+tysOOzuQBM9kqZCfFCvdZfcAAr0NMrSZbRJPxwSyVUnE1sI3G4hFQVWIhxjUH3aemXzNeVyHSNB9mnx/2fq70M3bF5hcyAy99px5KGP8Q7gXYw3EsmBZ9evtyqVYGF8gTpf70S4tdNc1SJLjcjkAzV1jCRZ5Yps= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2cc6ea4452cso41954551fa.1 for ; Wed, 20 Dec 2023 01:49:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1703065738; x=1703670538; darn=gcc.gnu.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=oMP1gC268B6XcFzYd1NG8AU+L3fDXPDTmhOsY1/Iw0I=; b=ZWxUXBWzQTdtiHtzK+wzCXpvyt0HaMTmy/imfA/0vGHsvPXnDpRYACbplWdMtWR2ml uLPVLtmdtRRnGUwGGT59DzKET3SAoDq2zEcHEY9FNjK0xP0FLIR+c1ABRDndWjaTm7nA ikN1g8b1ZmrMKfP64NVsLwu93CA/GcmthB7MnGk8wXGrZ49PoFjBoOZSwDlijiLMFfKx vHBo43/egiH48LuMhkh9apPup2YshCNGLp7Ldux95ps88+sY4yxXiJDCj2Oa1KyirpJJ aCAJBERCogr3LeVg3PGDIvHGWS9sd7LoipjW0MUV8uKkQuilXc9Z/H3cCnwSZPbWV0om VB/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703065738; x=1703670538; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=oMP1gC268B6XcFzYd1NG8AU+L3fDXPDTmhOsY1/Iw0I=; b=ukMIA51MZfwf/mXraa1JC0tFTSpjshZNx5nX3YNaNgTX0dbSHSxWDJKrNaXGQUxn2I IJZFLAei1F9vY+2ALR5k1zy2M3xS6oIuh6UwBFWaiWiWi+30paI9VNAG2Ac9OCxGsaER 9cCeO0eOgJ4gUnGrsQoC2Nobd9K4lYCI+bZOpMw//pjnsnqvZ7T18S0IKfzODrZdS7Te hoCFV6Rwh6seV3YSfFGyH2PrjRq8W2KK+KTQpB5SJ1tAynvgeMUNSlh+lyX9yHX+Dqs+ 6joVbTBvXwOcDWKFGoL8Znkov+93bYxWLM5Io3zCvzNTOQh/43XEOxaajfbiZVy29txG EwfA== X-Gm-Message-State: AOJu0YwSJHGyNZ65KASJyuqrFAu8Bv9wAOCNR2cnOY2EEaMDGAUZFQsi iQpWmR4o3lo7R40cvi8BTzISVBXDuYGCRmMSoW+Kv8UcfQI4xkbvB04hlQ== X-Google-Smtp-Source: AGHT+IGh/nWnw4krYbdxqPNlw7z0lF++dzwctLupADsqUjnhwrYtLofWkYoNYwXeTwJ0J3zH8mPo3Gg9zGMl4uBcmxE= X-Received: by 2002:a2e:a30b:0:b0:2cc:7111:7e39 with SMTP id l11-20020a2ea30b000000b002cc71117e39mr2180483lje.44.1703065738342; Wed, 20 Dec 2023 01:48:58 -0800 (PST) MIME-Version: 1.0 References: <20231219095348.356551-1-slewis@rivosinc.com> <20231219095348.356551-3-slewis@rivosinc.com> In-Reply-To: From: Sergei Lewis Date: Wed, 20 Dec 2023 09:48:47 +0000 Message-ID: Subject: Re: [PATCH v2 2/3] RISC-V: setmem for RISCV with V extension To: Jeff Law Cc: gcc-patches@gcc.gnu.org Content-Type: multipart/alternative; boundary="0000000000005d09aa060cede427" X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --0000000000005d09aa060cede427 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, This has been tested with the following configurations: rv64gcv_zvl128b rv64gcv_zvl256b rv32imafd_zve32x1p0 rv32gc_zve64f_zvl128b I'll drop the constraints and add the testing info to the cover email in v3. I'll hold off submitting v3 until gcc-15 as requested. On Wed, Dec 20, 2023 at 5:38=E2=80=AFAM Jeff Law wr= ote: > > > On 12/19/23 02:53, Sergei Lewis wrote: > > gcc/ChangeLog > > > > * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): > New function > > declaration. > > > > * config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): > New > > function: this generates an inline vectorised memory set, if and > only if we > > know the entire operation can be performed in a single vector store > > > > * config/riscv/riscv.md (setmem): Try > riscv_vector::expand_vec_setmem > > for constant lengths > > > > gcc/testsuite/ChangeLog > > * gcc.target/riscv/rvv/base/setmem-1.c: New tests > > * gcc.target/riscv/rvv/base/setmem-2.c: New tests > > * gcc.target/riscv/rvv/base/setmem-3.c: New tests > As with patch 1/3 this needs to be regression tested. The other > concern, which I should have voiced with patch 1/3 is that this was > submitted after the gcc-14 development window closed. While we do have > some degrees of freedom to accept backend specific new features, we > really shouldn't be adding new features/optimizations at this point. We > really should just be fixing bugs and new features should be queued for > gcc-15. > > > > > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > index 1b3f66fd15c..dd34211ca80 100644 > > --- a/gcc/config/riscv/riscv.md > > +++ b/gcc/config/riscv/riscv.md > > @@ -2387,6 +2387,20 @@ > > FAIL; > > }) > > > > +(define_expand "setmemsi" > > + [(set (match_operand:BLK 0 "memory_operand") ;; Dest > > + (match_operand:QI 2 "nonmemory_operand")) ;; Value > > + (use (match_operand:SI 1 "const_int_operand")) ;; Length > > + (match_operand:SI 3 "const_int_operand")] ;; Align > > + "TARGET_VECTOR" > > +{ > > + if (riscv_vector::expand_vec_setmem (operands[0], operands[1], > operands[2], > > + operands[3])) > > + DONE; > > + else > > + FAIL; > > +}) > Is the :SI really needed for operands1 and operands3? a CONST_INT node > never has a mode. Or is the existence of the mode just to keep the > gen* programs from generating a warning? And if we're going to keep a > mode, particularly on the length, shouldn't the length be in mode P? > > > Jeff > --0000000000005d09aa060cede427--