From 9939302480452cf179a7fd3176c3b411b80d3ad9 Mon Sep 17 00:00:00 2001
From: Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
Date: Thu, 17 Jan 2019 23:09:58 +1100
Subject: [PATCH] [SVE ACLE] Implements svdiv and svdivr

Change-Id: I4bc8fa5fc0015be0d773df77712d677010361ecf
---
 gcc/config/aarch64/aarch64-sve-builtins.c          |  50 ++-
 gcc/config/aarch64/aarch64-sve-builtins.def        |   2 +
 gcc/config/aarch64/aarch64-sve.md                  | 104 ++---
 .../gcc.target/aarch64/sve-acle/asm/div_f16.c      | 414 ++++++++++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/div_f32.c      | 414 ++++++++++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/div_f64.c      | 414 ++++++++++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/div_s32.c      | 254 ++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/div_s64.c      | 254 ++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/div_u32.c      | 254 ++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/div_u64.c      | 254 ++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/divr_f16.c     | 425 +++++++++++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/divr_f32.c     | 425 +++++++++++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/divr_f64.c     | 425 +++++++++++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/divr_s32.c     | 264 +++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/divr_s64.c     | 264 +++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/divr_u32.c     | 264 +++++++++++++
 .../gcc.target/aarch64/sve-acle/asm/divr_u64.c     | 264 +++++++++++++
 17 files changed, 4669 insertions(+), 76 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f16.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f32.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f64.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_s32.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_s64.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_u32.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_u64.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f16.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f32.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f64.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_s32.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_s64.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_u32.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_u64.c

diff --git a/gcc/config/aarch64/aarch64-sve-builtins.c b/gcc/config/aarch64/aarch64-sve-builtins.c
index d663de4..c039ceb 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins.c
+++ b/gcc/config/aarch64/aarch64-sve-builtins.c
@@ -158,6 +158,8 @@ enum function {
   FUNC_svabd,
   FUNC_svadd,
   FUNC_svasrd,
+  FUNC_svdiv,
+  FUNC_svdivr,
   FUNC_svdup,
   FUNC_svindex,
   FUNC_svmax,
@@ -451,6 +453,7 @@ private:
   rtx expand_abs ();
   rtx expand_add (unsigned int);
   rtx expand_asrd ();
+  rtx expand_div (bool);
   rtx expand_dup ();
   rtx expand_index ();
   rtx expand_max ();
@@ -469,7 +472,8 @@ private:
   rtx expand_sub (bool);
 
   rtx expand_pred_op (rtx_code, int);
-  rtx expand_signed_pred_op (rtx_code, rtx_code, int);
+  rtx expand_signed_pred_op (rtx_code, rtx_code, int,
+			     unsigned int = DEFAULT_MERGE_ARGNO);
   rtx expand_signed_pred_op (int, int, int);
   rtx expand_via_unpred_direct_optab (optab);
   rtx expand_via_unpred_insn (insn_code);
@@ -563,12 +567,22 @@ static const type_suffix_info type_suffixes[NUM_TYPE_SUFFIXES + 1] = {
 #define TYPES_all_integer(S, D) \
   TYPES_all_signed (S, D), TYPES_all_unsigned (S, D)
 
+/* _u32, _u64 _s32 _s64.  */
+#define TYPES_sdi(S, D) \
+  S (u32), S (u64), S (s32), S (s64)
+
 /*     _f16 _f32 _f64
    _u8 _u16 _u32 _u64
    _s8 _s16 _s32 _s64.  */
 #define TYPES_all_data(S, D) \
   TYPES_all_float (S, D), TYPES_all_integer (S, D)
 
+/* _f16 _f32 _f64
+        _u32 _u64
+        _s32 _s64.  */
+#define TYPES_all_sdi_and_float(S, D) \
+  TYPES_all_float (S, D), TYPES_sdi (S, D)
+
 /*     _f16 _f32 _f64
    _s8 _s16 _s32 _s64.  */
 #define TYPES_all_signed_and_float(S, D) \
@@ -594,6 +608,7 @@ DEF_SVE_TYPES_ARRAY (all_signed);
 DEF_SVE_TYPES_ARRAY (all_float);
 DEF_SVE_TYPES_ARRAY (all_integer);
 DEF_SVE_TYPES_ARRAY (all_data);
+DEF_SVE_TYPES_ARRAY (all_sdi_and_float);
 DEF_SVE_TYPES_ARRAY (all_signed_and_float);
 
 /* Used by functions in aarch64-sve-builtins.def that have no governing
@@ -1062,6 +1077,8 @@ arm_sve_h_builder::get_attributes (const function_instance &instance)
     case FUNC_svabs:
     case FUNC_svadd:
     case FUNC_svasrd:
+    case FUNC_svdiv:
+    case FUNC_svdivr:
     case FUNC_svdup:
     case FUNC_svindex:
     case FUNC_svmax:
@@ -1672,6 +1689,8 @@ gimple_folder::fold ()
     case FUNC_svabs:
     case FUNC_svadd:
     case FUNC_svasrd:
+    case FUNC_svdiv:
+    case FUNC_svdivr:
     case FUNC_svdup:
     case FUNC_svindex:
     case FUNC_svmax:
@@ -1756,6 +1775,12 @@ function_expander::expand ()
     case FUNC_svasrd:
       return expand_asrd ();
 
+    case FUNC_svdiv:
+      return expand_div (false);
+
+    case FUNC_svdivr:
+      return expand_div (true);
+
     case FUNC_svdup:
       return expand_dup ();
 
@@ -1853,6 +1878,20 @@ function_expander::expand_asrd ()
   return expand_pred_shift_right_imm (code_for_cond_asrd (get_mode (0)));
 }
 
+/* Expand a call to svdiv.  */
+rtx
+function_expander::expand_div (bool reversed_p)
+{
+  unsigned int merge_argno = 1;
+  if (reversed_p)
+    {
+      std::swap (m_args[1], m_args[2]);
+      merge_argno = 2;
+    }
+
+  return expand_signed_pred_op (DIV, UDIV, UNSPEC_COND_DIV, merge_argno);
+}
+
 /* Expand a call to svdup.  */
 rtx
 function_expander::expand_dup ()
@@ -2213,11 +2252,14 @@ function_expander::expand_pred_op (rtx_code code, int unspec_cond)
    the floating-point instructions are parameterized by an unspec code.
    CODE_FOR_SINT is the rtx_code for signed integer operations,
    CODE_FOR_UINT is the rtx_code for unsigned integer operations
-   and UNSPEC_COND is the unspec code for floating-point operations.  */
+   and UNSPEC_COND is the unspec code for floating-point operations.
+   MERGE_ARGNO is the argument that should be used as the fallback
+   value in a merging operation.  */
 rtx
 function_expander::expand_signed_pred_op (rtx_code code_for_sint,
 					  rtx_code code_for_uint,
-					  int unspec_cond)
+					  int unspec_cond,
+					  unsigned int merge_argno)
 {
   insn_code icode;
 
@@ -2245,7 +2287,7 @@ function_expander::expand_signed_pred_op (rtx_code code_for_sint,
 	}
       else
 	icode = code_for_cond (unspec_cond, get_mode (0));
-      return expand_via_pred_insn (icode);
+      return expand_via_pred_insn (icode, merge_argno);
     }
 }
 
diff --git a/gcc/config/aarch64/aarch64-sve-builtins.def b/gcc/config/aarch64/aarch64-sve-builtins.def
index 83dc8e5..2d840da 100644
--- a/gcc/config/aarch64/aarch64-sve-builtins.def
+++ b/gcc/config/aarch64/aarch64-sve-builtins.def
@@ -64,6 +64,8 @@ DEF_SVE_FUNCTION (svabd, binary_opt_n, all_data, mxz)
 DEF_SVE_FUNCTION (svabs, unary, all_signed_and_float, mxz)
 DEF_SVE_FUNCTION (svadd, binary_opt_n, all_data, mxz)
 DEF_SVE_FUNCTION (svasrd, shift_right_imm, all_signed, mxz)
+DEF_SVE_FUNCTION (svdiv, binary_opt_n, all_sdi_and_float, mxz)
+DEF_SVE_FUNCTION (svdivr, binary_opt_n, all_sdi_and_float, mxz)
 DEF_SVE_FUNCTION (svdup, unary_n, all_data, mxznone)
 DEF_SVE_FUNCTION (svindex, binary_scalar, all_data, none)
 DEF_SVE_FUNCTION (svmax, binary_opt_n, all_data, mxz)
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index d8ec4ad..944de82 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -1241,13 +1241,13 @@
 )
 
 ;; Division predicated with a PTRUE.
-(define_insn "*<optab><mode>3"
+(define_insn "@aarch64_pred_<optab><mode>"
   [(set (match_operand:SVE_SDI 0 "register_operand" "=w, w, ?&w")
 	(unspec:SVE_SDI
 	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
 	   (SVE_INT_BINARY_SD:SVE_SDI
 	     (match_operand:SVE_SDI 2 "register_operand" "0, w, w")
-	     (match_operand:SVE_SDI 3 "aarch64_sve_mul_operand" "w, 0, w"))]
+	     (match_operand:SVE_SDI 3 "register_operand" "w, 0, w"))]
 	  UNSPEC_MERGE_PTRUE))]
   "TARGET_SVE"
   "@
@@ -2015,63 +2015,50 @@
 )
 
 ;; Unpredicated floating-point MIN/MAX.
-(define_expand "<su><maxmin><mode>3"
+(define_expand "<maxmin_uns><mode>3"
   [(set (match_operand:SVE_F 0 "register_operand")
 	(unspec:SVE_F
 	  [(match_dup 3)
-	   (FMAXMIN:SVE_F (match_operand:SVE_F 1 "register_operand")
-			  (match_operand:SVE_F 2 "register_operand"))]
-	  UNSPEC_MERGE_PTRUE))]
+	   (const_int SVE_ALLOW_NEW_FAULTS)
+	   (match_operand:SVE_F 1 "register_operand")
+	   (match_operand:SVE_F 2 "register_operand")]
+	  SVE_COND_MAXMIN))]
   "TARGET_SVE"
   {
     operands[3] = force_reg (<VPRED>mode, CONSTM1_RTX (<VPRED>mode));
   }
 )
 
-;; Floating-point MIN/MAX predicated with a PTRUE.
-(define_insn "*<su><maxmin><mode>3"
-  [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w")
-	(unspec:SVE_F
-	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
-	   (FMAXMIN:SVE_F (match_operand:SVE_F 2 "register_operand" "%0, w")
-			  (match_operand:SVE_F 3 "register_operand" "w, w"))]
-	  UNSPEC_MERGE_PTRUE))]
-  "TARGET_SVE"
-  "@
-   f<maxmin>nm\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
-   movprfx\t%0, %2\;f<maxmin>nm\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
-  [(set_attr "movprfx" "*,yes")]
-)
-
-;; Unpredicated fmin/fmax.
-(define_expand "<maxmin_uns><mode>3"
+;; Unpredicated floating-point binary operations that have no immediate forms.
+(define_expand "<optab><mode>3"
   [(set (match_operand:SVE_F 0 "register_operand")
 	(unspec:SVE_F
 	  [(match_dup 3)
 	   (const_int SVE_ALLOW_NEW_FAULTS)
 	   (match_operand:SVE_F 1 "register_operand")
 	   (match_operand:SVE_F 2 "register_operand")]
-	  SVE_COND_MAXMIN))]
+	  SVE_COND_FP_BINARY))]
   "TARGET_SVE"
   {
     operands[3] = force_reg (<VPRED>mode, CONSTM1_RTX (<VPRED>mode));
   }
 )
 
-;; Predicated FMIN, FMAX, FMINNM and FMAXNM.
-(define_insn "@aarch64_pred_<maxmin_uns><mode>"
-  [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w")
+;; Predicated floating-point binary operations that have no immediate forms.
+(define_insn "@aarch64_pred_<optab><mode>"
+  [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w")
 	(unspec:SVE_F
-	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
-	   (match_operand:SI 4 "const_int_operand" "i, i")
-	   (match_operand:SVE_F 2 "register_operand" "%0, w")
-	   (match_operand:SVE_F 3 "register_operand" "w, w")]
-	  SVE_COND_MAXMIN))]
+	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
+	   (match_operand:SI 4 "const_int_operand" "i, i, i")
+	   (match_operand:SVE_F 2 "register_operand" "0, w, w")
+	   (match_operand:SVE_F 3 "register_operand" "w, 0, w")]
+	  SVE_COND_FP_BINARY))]
   "TARGET_SVE"
   "@
-   <maxmin_uns_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
-   movprfx\t%0, %2\;<maxmin_uns_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
-  [(set_attr "movprfx" "*,yes")]
+   <sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
+   <sve_fp_op_rev>\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>
+   movprfx\t%0, %2\;<sve_fp_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
+  [(set_attr "movprfx" "*,*,yes")]
 )
 
 ;; Predicated SABD and UABD.
@@ -2250,7 +2237,7 @@
  [(set_attr "movprfx" "*,yes,*")]
 )
 
-(define_expand "cond_<optab><mode>"
+(define_expand "@cond_<optab><mode>"
   [(set (match_operand:SVE_SDI 0 "register_operand")
 	(unspec:SVE_SDI
 	  [(match_operand:<VPRED> 1 "register_operand")
@@ -2382,16 +2369,19 @@
 )
 
 (define_insn "*cond_<optab><mode>_z"
-  [(set (match_operand:SVE_SDI 0 "register_operand" "=&w,w")
+  [(set (match_operand:SVE_SDI 0 "register_operand" "=&w,&w,&w")
 	(unspec:SVE_SDI
-	  [(match_operand:<VPRED> 1 "register_operand" "Upl,Upl")
+	  [(match_operand:<VPRED> 1 "register_operand" "Upl,Upl,Upl")
 	   (SVE_INT_BINARY_SD:SVE_SDI
-	     (match_operand:SVE_SDI 2 "register_operand" "0,w")
-	     (match_operand:SVE_SDI 3 "register_operand" "w,w"))
+	     (match_operand:SVE_SDI 2 "register_operand" "0,w,w")
+	     (match_operand:SVE_SDI 3 "register_operand" "w,0,w"))
 	   (match_operand:SVE_SDI 4 "aarch64_simd_imm_zero")]
 	  UNSPEC_SEL))]
   "TARGET_SVE"
-  "movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
+  "@
+   movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
+   movprfx\t%0.<Vetype>, %1/z, %0.<Vetype>\;<sve_int_op_rev>\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>
+   movprfx\t%0.<Vetype>, %1/z, %2.<Vetype>\;<sve_int_op>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
   [(set_attr "movprfx" "yes")]
 )
 
@@ -2459,7 +2449,7 @@
   [(set (match_operand:SVE_SDI 0 "register_operand" "=&w")
 	(unspec:SVE_SDI
 	  [(match_operand:<VPRED> 1 "register_operand" "Upl")
-	   (SVE_INT_BINARY_SD:SVE_I
+	   (SVE_INT_BINARY_SD:SVE_SDI
 	     (match_operand:SVE_SDI 2 "register_operand" "w")
 	     (match_operand:SVE_SDI 3 "register_operand" "w"))
 	   (match_operand:SVE_SDI 4 "register_operand"   "w")]
@@ -2845,36 +2835,6 @@
   [(set_attr "movprfx" "*,*,*,yes")]
 )
 
-;; Unpredicated floating-point division.
-(define_expand "div<mode>3"
-  [(set (match_operand:SVE_F 0 "register_operand")
-	(unspec:SVE_F
-	  [(match_dup 3)
-	   (div:SVE_F (match_operand:SVE_F 1 "register_operand")
-		      (match_operand:SVE_F 2 "register_operand"))]
-	  UNSPEC_MERGE_PTRUE))]
-  "TARGET_SVE"
-  {
-    operands[3] = force_reg (<VPRED>mode, CONSTM1_RTX (<VPRED>mode));
-  }
-)
-
-;; Floating-point division predicated with a PTRUE.
-(define_insn "*div<mode>3"
-  [(set (match_operand:SVE_F 0 "register_operand" "=w, w, ?&w")
-	(unspec:SVE_F
-	  [(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
-	   (div:SVE_F (match_operand:SVE_F 2 "register_operand" "0, w, w")
-		      (match_operand:SVE_F 3 "register_operand" "w, 0, w"))]
-	  UNSPEC_MERGE_PTRUE))]
-  "TARGET_SVE"
-  "@
-   fdiv\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>
-   fdivr\t%0.<Vetype>, %1/m, %0.<Vetype>, %2.<Vetype>
-   movprfx\t%0, %2\;fdiv\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
-  [(set_attr "movprfx" "*,*,yes")]
-)
-
 ;; Unpredicated FNEG, FABS and FSQRT.
 (define_expand "<optab><mode>2"
   [(set (match_operand:SVE_F 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f16.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f16.c
new file mode 100644
index 0000000..54e0956
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f16.c
@@ -0,0 +1,414 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** div_f16_m_tied1:
+**	fdiv	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_f16_m_tied1, svfloat16_t,
+		z0 = svdiv_f16_m (p0, z0, z1),
+		z0 = svdiv_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (div_f16_m_tied2, svfloat16_t,
+		z1 = svdiv_f16_m (p0, z0, z1),
+		z1 = svdiv_m (p0, z0, z1))
+
+/*
+** div_f16_m_untied:
+**	movprfx	z0, z1
+**	fdiv	z0\.h, p0/m, z0\.h, z2\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_f16_m_untied, svfloat16_t,
+		z0 = svdiv_f16_m (p0, z1, z2),
+		z0 = svdiv_m (p0, z1, z2))
+
+/*
+** div_w0_f16_m_tied1:
+**	mov	(z[0-9]+\.h), w0
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f16_m_tied1, svfloat16_t, __fp16,
+		 z0 = svdiv_n_f16_m (p0, z0, x0),
+		 z0 = svdiv_m (p0, z0, x0))
+
+/*
+** div_w0_f16_m_untied:
+**	mov	(z[0-9]+\.h), w0
+**	movprfx	z0, z1
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f16_m_untied, svfloat16_t, __fp16,
+		 z0 = svdiv_n_f16_m (p0, z1, x0),
+		 z0 = svdiv_m (p0, z1, x0))
+
+/*
+** div_h0_f16_m_tied1:
+**	mov	(z[0-9]+\.h), h0
+**	fdiv	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_h0_f16_m_tied1, svfloat16_t, __fp16,
+		 z1 = svdiv_n_f16_m (p0, z1, d0),
+		 z1 = svdiv_m (p0, z1, d0))
+
+/*
+** div_h0_f16_m_untied:
+**	mov	(z[0-9]+\.h), h0
+**	movprfx	z1, z2
+**	fdiv	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_h0_f16_m_untied, svfloat16_t, __fp16,
+		 z1 = svdiv_n_f16_m (p0, z2, d0),
+		 z1 = svdiv_m (p0, z2, d0))
+
+/*
+** div_1_f16_m_tied1:
+**	fmov	(z[0-9]+\.h), #1.0(e\+0)?
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f16_m_tied1, svfloat16_t,
+		z0 = svdiv_n_f16_m (p0, z0, 1),
+		z0 = svdiv_m (p0, z0, 1))
+
+/*
+** div_1_f16_m_untied:
+**	fmov	(z[0-9]+\.h), #1.0(e\+0)?
+**	movprfx	z0, z1
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f16_m_untied, svfloat16_t,
+		z0 = svdiv_n_f16_m (p0, z1, 1),
+		z0 = svdiv_m (p0, z1, 1))
+
+/*
+** div_f16_z_tied1:
+**	movprfx	z0\.h, p0/z, z0\.h
+**	fdiv	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_f16_z_tied1, svfloat16_t,
+		z0 = svdiv_f16_z (p0, z0, z1),
+		z0 = svdiv_z (p0, z0, z1))
+
+/*
+** div_f16_z_tied2:
+**	movprfx	z1\.h, p0/z, z1\.h
+**	fdivr	z1\.h, p0/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_f16_z_tied2, svfloat16_t,
+		z1 = svdiv_f16_z (p0, z0, z1),
+		z1 = svdiv_z (p0, z0, z1))
+
+/*
+** div_f16_z_untied:
+**	movprfx	z0\.h, p0/z, z1\.h
+**	fdiv	z0\.h, p0/m, z0\.h, z2\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_f16_z_untied, svfloat16_t,
+		z0 = svdiv_f16_z (p0, z1, z2),
+		z0 = svdiv_z (p0, z1, z2))
+
+/*
+** div_w0_f16_z_tied1:
+**	mov	(z[0-9]+\.h), w0
+**	movprfx	z0\.h, p0/z, z0\.h
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f16_z_tied1, svfloat16_t, __fp16,
+		 z0 = svdiv_n_f16_z (p0, z0, x0),
+		 z0 = svdiv_z (p0, z0, x0))
+
+/*
+** div_w0_f16_z_untied:
+**	mov	(z[0-9]+\.h), w0
+**	movprfx	z0\.h, p0/z, z1\.h
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f16_z_untied, svfloat16_t, __fp16,
+		 z0 = svdiv_n_f16_z (p0, z1, x0),
+		 z0 = svdiv_z (p0, z1, x0))
+
+/*
+** div_h0_f16_z_tied1:
+**	mov	(z[0-9]+\.h), h0
+**	movprfx	z1\.h, p0/z, z1\.h
+**	fdiv	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_h0_f16_z_tied1, svfloat16_t, __fp16,
+		 z1 = svdiv_n_f16_z (p0, z1, d0),
+		 z1 = svdiv_z (p0, z1, d0))
+
+/*
+** div_h0_f16_z_untied:
+**	mov	(z[0-9]+\.h), h0
+**	movprfx	z1\.h, p0/z, z2\.h
+**	fdiv	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_h0_f16_z_untied, svfloat16_t, __fp16,
+		 z1 = svdiv_n_f16_z (p0, z2, d0),
+		 z1 = svdiv_z (p0, z2, d0))
+
+/*
+** div_1_f16_z_tied1:
+**	fmov	(z[0-9]+\.h), #1.0(e\+0)?
+**	movprfx	z0\.h, p0/z, z0\.h
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f16_z_tied1, svfloat16_t,
+		z0 = svdiv_n_f16_z (p0, z0, 1),
+		z0 = svdiv_z (p0, z0, 1))
+
+/*
+** div_1_f16_z_untied:
+**	fmov	(z[0-9]+\.h), #1.0(e\+0)?
+**	movprfx	z1\.h, p0/z, z0\.h
+**	fdiv	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f16_z_untied, svfloat16_t,
+		z1 = svdiv_n_f16_z (p0, z0, 1),
+		z1 = svdiv_z (p0, z0, 1))
+
+/*
+** div_0p5_f16_z_untied:
+**	fmov	(z[0-9]+\.h), #5.0(e\-1)?
+**	movprfx	z0\.h, p0/z, z1\.h
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_0p5_f16_z_untied, svfloat16_t,
+		z0 = svdiv_n_f16_z (p0, z1, 0.5),
+		z0 = svdiv_z (p0, z1, 0.5))
+
+/*
+** div_f16_x_tied1:
+**	fdiv	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_f16_x_tied1, svfloat16_t,
+		z0 = svdiv_f16_x (p0, z0, z1),
+		z0 = svdiv_x (p0, z0, z1))
+
+/*
+** div_f16_x_tied2:
+**	fdivr	z1\.h, p0/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_f16_x_tied2, svfloat16_t,
+		z1 = svdiv_f16_x (p0, z0, z1),
+		z1 = svdiv_x (p0, z0, z1))
+
+/*
+** div_f16_x_untied:
+**	movprfx	z2, z0
+**	fdiv	z2\.h, p0/m, z2\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_f16_x_untied, svfloat16_t,
+		z2 = svdiv_f16_x (p0, z0, z1),
+		z2 = svdiv_x (p0, z0, z1))
+
+/*
+** div_w0_f16_x_tied1:
+**	mov	(z[0-9]+\.h), w0
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f16_x_tied1, svfloat16_t, __fp16,
+		 z0 = svdiv_n_f16_x (p0, z0, x0),
+		 z0 = svdiv_x (p0, z0, x0))
+
+/*
+** div_w0_f16_x_untied:
+**	mov	z1\.h, w0
+**	fdivr	z1\.h, p0/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f16_x_untied, svfloat16_t, __fp16,
+		 z1 = svdiv_n_f16_x (p0, z0, x0),
+		 z1 = svdiv_x (p0, z0, x0))
+
+/*
+** div_h0_f16_x_tied1:
+**	mov	(z[0-9]+\.h), h0
+**	fdiv	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_h0_f16_x_tied1, svfloat16_t, __fp16,
+		 z1 = svdiv_n_f16_x (p0, z1, d0),
+		 z1 = svdiv_x (p0, z1, d0))
+
+/*
+** div_h0_f16_x_untied:
+**	mov	z2\.h, h0
+**	fdivr	z2\.h, p0/m, z2\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (div_h0_f16_x_untied, svfloat16_t, __fp16,
+		 z2 = svdiv_n_f16_x (p0, z1, d0),
+		 z2 = svdiv_x (p0, z1, d0))
+
+/*
+** div_1_f16_x_tied1:
+**	fmov	(z[0-9]+\.h), #1\.0(e\+0)?
+**	fdiv	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f16_x_tied1, svfloat16_t,
+		z0 = svdiv_n_f16_x (p0, z0, 1),
+		z0 = svdiv_x (p0, z0, 1))
+
+/*
+** div_1_f16_x_untied:
+**	fmov	z0\.h, #1\.0(e\+0)?
+**	fdivr	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f16_x_untied, svfloat16_t,
+		z0 = svdiv_n_f16_x (p0, z1, 1),
+		z0 = svdiv_x (p0, z1, 1))
+
+/*
+** ptrue_div_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fdiv	z0\.h, \1/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f16_x_tied1, svfloat16_t,
+		z0 = svdiv_f16_x (svptrue_b16 (), z0, z1),
+		z0 = svdiv_x (svptrue_b16 (), z0, z1))
+
+/*
+** ptrue_div_f16_x_tied2:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fdivr	z1\.h, \1/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f16_x_tied2, svfloat16_t,
+		z1 = svdiv_f16_x (svptrue_b16 (), z0, z1),
+		z1 = svdiv_x (svptrue_b16 (), z0, z1))
+
+/*
+** ptrue_div_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	movprfx	z2, z0
+**	fdiv	z2\.h, \1/m, z2\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f16_x_untied, svfloat16_t,
+		z2 = svdiv_f16_x (svptrue_b16 (), z0, z1),
+		z2 = svdiv_x (svptrue_b16 (), z0, z1))
+
+/*
+** ptrue_div_w0_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	mov	(z[0-9]+\.h), w0
+**	fdiv	z0\.h, \1/m, z0\.h, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_w0_f16_x_tied1, svfloat16_t, __fp16,
+		 z0 = svdiv_n_f16_x (svptrue_b16 (), z0, x0),
+		 z0 = svdiv_x (svptrue_b16 (), z0, x0))
+
+/*
+** ptrue_div_w0_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	mov	z1\.h, w0
+**	fdivr	z1\.h, \1/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_w0_f16_x_untied, svfloat16_t, __fp16,
+		 z1 = svdiv_n_f16_x (svptrue_b16 (), z0, x0),
+		 z1 = svdiv_x (svptrue_b16 (), z0, x0))
+
+/*
+** ptrue_div_h0_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	mov	(z[0-9]+\.h), h0
+**	fdiv	z1\.h, \1/m, z1\.h, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_h0_f16_x_tied1, svfloat16_t, __fp16,
+		 z1 = svdiv_n_f16_x (svptrue_b16 (), z1, d0),
+		 z1 = svdiv_x (svptrue_b16 (), z1, d0))
+
+/*
+** ptrue_div_h0_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	mov	z2\.h, h0
+**	fdivr	z2\.h, \1/m, z2\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_h0_f16_x_untied, svfloat16_t, __fp16,
+		 z2 = svdiv_n_f16_x (svptrue_b16 (), z1, d0),
+		 z2 = svdiv_x (svptrue_b16 (), z1, d0))
+
+/*
+** ptrue_div_1_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fmov	z0\.h, #1.0(e\+0)?
+**	fdivr	z0\.h, \1/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_1_f16_x_untied, svfloat16_t,
+		z0 = svdiv_n_f16_x (svptrue_b16 (), z1, 1),
+		z0 = svdiv_x (svptrue_b16 (), z1, 1))
+
+/*
+** ptrue_div_1_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fmov	(z[0-9]+\.h), #1.0(e\+0)?
+**	fdiv	z1\.h, \1/m, z1\.h, \2
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_1_f16_x_tied1, svfloat16_t,
+		z1 = svdiv_n_f16_x (svptrue_b16 (), z1, 1),
+		z1 = svdiv_x (svptrue_b16 (), z1, 1))
+
+/*
+** ptrue_b8_div_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fdiv	z0\.h, \1/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f16_x_tied1, svfloat16_t,
+		z0 = svdiv_f16_x (svptrue_b8 (), z0, z1),
+		z0 = svdiv_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_div_f16_x_tied2:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fdivr	z1\.h, \1/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f16_x_tied2, svfloat16_t,
+		z1 = svdiv_f16_x (svptrue_b8 (), z0, z1),
+		z1 = svdiv_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_div_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	movprfx	z2, z0
+**	fdiv	z2\.h, \1/m, z2\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f16_x_untied, svfloat16_t,
+		z2 = svdiv_f16_x (svptrue_b8 (), z0, z1),
+		z2 = svdiv_x (svptrue_b8 (), z0, z1))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f32.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f32.c
new file mode 100644
index 0000000..1764610
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f32.c
@@ -0,0 +1,414 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** div_f32_m_tied1:
+**	fdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_f32_m_tied1, svfloat32_t,
+		z0 = svdiv_f32_m (p0, z0, z1),
+		z0 = svdiv_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (div_f32_m_tied2, svfloat32_t,
+		z1 = svdiv_f32_m (p0, z0, z1),
+		z1 = svdiv_m (p0, z0, z1))
+
+/*
+** div_f32_m_untied:
+**	movprfx	z0, z1
+**	fdiv	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_f32_m_untied, svfloat32_t,
+		z0 = svdiv_f32_m (p0, z1, z2),
+		z0 = svdiv_m (p0, z1, z2))
+
+/*
+** div_w0_f32_m_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f32_m_tied1, svfloat32_t, float,
+		 z0 = svdiv_n_f32_m (p0, z0, x0),
+		 z0 = svdiv_m (p0, z0, x0))
+
+/*
+** div_w0_f32_m_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0, z1
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f32_m_untied, svfloat32_t, float,
+		 z0 = svdiv_n_f32_m (p0, z1, x0),
+		 z0 = svdiv_m (p0, z1, x0))
+
+/*
+** div_s0_f32_m_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	fdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_f32_m_tied1, svfloat32_t, float,
+		 z1 = svdiv_n_f32_m (p0, z1, d0),
+		 z1 = svdiv_m (p0, z1, d0))
+
+/*
+** div_s0_f32_m_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1, z2
+**	fdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_f32_m_untied, svfloat32_t, float,
+		 z1 = svdiv_n_f32_m (p0, z2, d0),
+		 z1 = svdiv_m (p0, z2, d0))
+
+/*
+** div_1_f32_m_tied1:
+**	fmov	(z[0-9]+\.s), #1.0(e\+0)?
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f32_m_tied1, svfloat32_t,
+		z0 = svdiv_n_f32_m (p0, z0, 1),
+		z0 = svdiv_m (p0, z0, 1))
+
+/*
+** div_1_f32_m_untied:
+**	fmov	(z[0-9]+\.s), #1.0(e\+0)?
+**	movprfx	z0, z1
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f32_m_untied, svfloat32_t,
+		z0 = svdiv_n_f32_m (p0, z1, 1),
+		z0 = svdiv_m (p0, z1, 1))
+
+/*
+** div_f32_z_tied1:
+**	movprfx	z0\.s, p0/z, z0\.s
+**	fdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_f32_z_tied1, svfloat32_t,
+		z0 = svdiv_f32_z (p0, z0, z1),
+		z0 = svdiv_z (p0, z0, z1))
+
+/*
+** div_f32_z_tied2:
+**	movprfx	z1\.s, p0/z, z1\.s
+**	fdivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_f32_z_tied2, svfloat32_t,
+		z1 = svdiv_f32_z (p0, z0, z1),
+		z1 = svdiv_z (p0, z0, z1))
+
+/*
+** div_f32_z_untied:
+**	movprfx	z0\.s, p0/z, z1\.s
+**	fdiv	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_f32_z_untied, svfloat32_t,
+		z0 = svdiv_f32_z (p0, z1, z2),
+		z0 = svdiv_z (p0, z1, z2))
+
+/*
+** div_w0_f32_z_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z0\.s
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f32_z_tied1, svfloat32_t, float,
+		 z0 = svdiv_n_f32_z (p0, z0, x0),
+		 z0 = svdiv_z (p0, z0, x0))
+
+/*
+** div_w0_f32_z_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z1\.s
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f32_z_untied, svfloat32_t, float,
+		 z0 = svdiv_n_f32_z (p0, z1, x0),
+		 z0 = svdiv_z (p0, z1, x0))
+
+/*
+** div_s0_f32_z_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z1\.s
+**	fdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_f32_z_tied1, svfloat32_t, float,
+		 z1 = svdiv_n_f32_z (p0, z1, d0),
+		 z1 = svdiv_z (p0, z1, d0))
+
+/*
+** div_s0_f32_z_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z2\.s
+**	fdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_f32_z_untied, svfloat32_t, float,
+		 z1 = svdiv_n_f32_z (p0, z2, d0),
+		 z1 = svdiv_z (p0, z2, d0))
+
+/*
+** div_1_f32_z_tied1:
+**	fmov	(z[0-9]+\.s), #1.0(e\+0)?
+**	movprfx	z0\.s, p0/z, z0\.s
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f32_z_tied1, svfloat32_t,
+		z0 = svdiv_n_f32_z (p0, z0, 1),
+		z0 = svdiv_z (p0, z0, 1))
+
+/*
+** div_1_f32_z_untied:
+**	fmov	(z[0-9]+\.s), #1.0(e\+0)?
+**	movprfx	z1\.s, p0/z, z0\.s
+**	fdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f32_z_untied, svfloat32_t,
+		z1 = svdiv_n_f32_z (p0, z0, 1),
+		z1 = svdiv_z (p0, z0, 1))
+
+/*
+** div_0p5_f32_z_untied:
+**	fmov	(z[0-9]+\.s), #5.0(e\-1)?
+**	movprfx	z0\.s, p0/z, z1\.s
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_0p5_f32_z_untied, svfloat32_t,
+		z0 = svdiv_n_f32_z (p0, z1, 0.5),
+		z0 = svdiv_z (p0, z1, 0.5))
+
+/*
+** div_f32_x_tied1:
+**	fdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_f32_x_tied1, svfloat32_t,
+		z0 = svdiv_f32_x (p0, z0, z1),
+		z0 = svdiv_x (p0, z0, z1))
+
+/*
+** div_f32_x_tied2:
+**	fdivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_f32_x_tied2, svfloat32_t,
+		z1 = svdiv_f32_x (p0, z0, z1),
+		z1 = svdiv_x (p0, z0, z1))
+
+/*
+** div_f32_x_untied:
+**	movprfx	z2, z0
+**	fdiv	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_f32_x_untied, svfloat32_t,
+		z2 = svdiv_f32_x (p0, z0, z1),
+		z2 = svdiv_x (p0, z0, z1))
+
+/*
+** div_w0_f32_x_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f32_x_tied1, svfloat32_t, float,
+		 z0 = svdiv_n_f32_x (p0, z0, x0),
+		 z0 = svdiv_x (p0, z0, x0))
+
+/*
+** div_w0_f32_x_untied:
+**	mov	z1\.s, w0
+**	fdivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_f32_x_untied, svfloat32_t, float,
+		 z1 = svdiv_n_f32_x (p0, z0, x0),
+		 z1 = svdiv_x (p0, z0, x0))
+
+/*
+** div_s0_f32_x_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	fdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_f32_x_tied1, svfloat32_t, float,
+		 z1 = svdiv_n_f32_x (p0, z1, d0),
+		 z1 = svdiv_x (p0, z1, d0))
+
+/*
+** div_s0_f32_x_untied:
+**	mov	z2\.s, s0
+**	fdivr	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_f32_x_untied, svfloat32_t, float,
+		 z2 = svdiv_n_f32_x (p0, z1, d0),
+		 z2 = svdiv_x (p0, z1, d0))
+
+/*
+** div_1_f32_x_tied1:
+**	fmov	(z[0-9]+\.s), #1\.0(e\+0)?
+**	fdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f32_x_tied1, svfloat32_t,
+		z0 = svdiv_n_f32_x (p0, z0, 1),
+		z0 = svdiv_x (p0, z0, 1))
+
+/*
+** div_1_f32_x_untied:
+**	fmov	z0\.s, #1\.0(e\+0)?
+**	fdivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f32_x_untied, svfloat32_t,
+		z0 = svdiv_n_f32_x (p0, z1, 1),
+		z0 = svdiv_x (p0, z1, 1))
+
+/*
+** ptrue_div_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fdiv	z0\.s, \1/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f32_x_tied1, svfloat32_t,
+		z0 = svdiv_f32_x (svptrue_b32 (), z0, z1),
+		z0 = svdiv_x (svptrue_b32 (), z0, z1))
+
+/*
+** ptrue_div_f32_x_tied2:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fdivr	z1\.s, \1/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f32_x_tied2, svfloat32_t,
+		z1 = svdiv_f32_x (svptrue_b32 (), z0, z1),
+		z1 = svdiv_x (svptrue_b32 (), z0, z1))
+
+/*
+** ptrue_div_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	movprfx	z2, z0
+**	fdiv	z2\.s, \1/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f32_x_untied, svfloat32_t,
+		z2 = svdiv_f32_x (svptrue_b32 (), z0, z1),
+		z2 = svdiv_x (svptrue_b32 (), z0, z1))
+
+/*
+** ptrue_div_w0_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	mov	(z[0-9]+\.s), w0
+**	fdiv	z0\.s, \1/m, z0\.s, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_w0_f32_x_tied1, svfloat32_t, float,
+		 z0 = svdiv_n_f32_x (svptrue_b32 (), z0, x0),
+		 z0 = svdiv_x (svptrue_b32 (), z0, x0))
+
+/*
+** ptrue_div_w0_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	mov	z1\.s, w0
+**	fdivr	z1\.s, \1/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_w0_f32_x_untied, svfloat32_t, float,
+		 z1 = svdiv_n_f32_x (svptrue_b32 (), z0, x0),
+		 z1 = svdiv_x (svptrue_b32 (), z0, x0))
+
+/*
+** ptrue_div_s0_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	mov	(z[0-9]+\.s), s0
+**	fdiv	z1\.s, \1/m, z1\.s, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_s0_f32_x_tied1, svfloat32_t, float,
+		 z1 = svdiv_n_f32_x (svptrue_b32 (), z1, d0),
+		 z1 = svdiv_x (svptrue_b32 (), z1, d0))
+
+/*
+** ptrue_div_s0_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	mov	z2\.s, s0
+**	fdivr	z2\.s, \1/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_s0_f32_x_untied, svfloat32_t, float,
+		 z2 = svdiv_n_f32_x (svptrue_b32 (), z1, d0),
+		 z2 = svdiv_x (svptrue_b32 (), z1, d0))
+
+/*
+** ptrue_div_1_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fmov	z0\.s, #1.0(e\+0)?
+**	fdivr	z0\.s, \1/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_1_f32_x_untied, svfloat32_t,
+		z0 = svdiv_n_f32_x (svptrue_b32 (), z1, 1),
+		z0 = svdiv_x (svptrue_b32 (), z1, 1))
+
+/*
+** ptrue_div_1_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fmov	(z[0-9]+\.s), #1.0(e\+0)?
+**	fdiv	z1\.s, \1/m, z1\.s, \2
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_1_f32_x_tied1, svfloat32_t,
+		z1 = svdiv_n_f32_x (svptrue_b32 (), z1, 1),
+		z1 = svdiv_x (svptrue_b32 (), z1, 1))
+
+/*
+** ptrue_b8_div_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fdiv	z0\.s, \1/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f32_x_tied1, svfloat32_t,
+		z0 = svdiv_f32_x (svptrue_b8 (), z0, z1),
+		z0 = svdiv_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_div_f32_x_tied2:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fdivr	z1\.s, \1/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f32_x_tied2, svfloat32_t,
+		z1 = svdiv_f32_x (svptrue_b8 (), z0, z1),
+		z1 = svdiv_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_div_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	movprfx	z2, z0
+**	fdiv	z2\.s, \1/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f32_x_untied, svfloat32_t,
+		z2 = svdiv_f32_x (svptrue_b8 (), z0, z1),
+		z2 = svdiv_x (svptrue_b8 (), z0, z1))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f64.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f64.c
new file mode 100644
index 0000000..c679dd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_f64.c
@@ -0,0 +1,414 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** div_f64_m_tied1:
+**	fdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_f64_m_tied1, svfloat64_t,
+		z0 = svdiv_f64_m (p0, z0, z1),
+		z0 = svdiv_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (div_f64_m_tied2, svfloat64_t,
+		z1 = svdiv_f64_m (p0, z0, z1),
+		z1 = svdiv_m (p0, z0, z1))
+
+/*
+** div_f64_m_untied:
+**	movprfx	z0, z1
+**	fdiv	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_f64_m_untied, svfloat64_t,
+		z0 = svdiv_f64_m (p0, z1, z2),
+		z0 = svdiv_m (p0, z1, z2))
+
+/*
+** div_x0_f64_m_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_f64_m_tied1, svfloat64_t, double,
+		 z0 = svdiv_n_f64_m (p0, z0, x0),
+		 z0 = svdiv_m (p0, z0, x0))
+
+/*
+** div_x0_f64_m_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0, z1
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_f64_m_untied, svfloat64_t, double,
+		 z0 = svdiv_n_f64_m (p0, z1, x0),
+		 z0 = svdiv_m (p0, z1, x0))
+
+/*
+** div_d0_f64_m_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	fdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_f64_m_tied1, svfloat64_t, double,
+		 z1 = svdiv_n_f64_m (p0, z1, d0),
+		 z1 = svdiv_m (p0, z1, d0))
+
+/*
+** div_d0_f64_m_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1, z2
+**	fdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_f64_m_untied, svfloat64_t, double,
+		 z1 = svdiv_n_f64_m (p0, z2, d0),
+		 z1 = svdiv_m (p0, z2, d0))
+
+/*
+** div_1_f64_m_tied1:
+**	fmov	(z[0-9]+\.d), #1.0(e\+0)?
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f64_m_tied1, svfloat64_t,
+		z0 = svdiv_n_f64_m (p0, z0, 1),
+		z0 = svdiv_m (p0, z0, 1))
+
+/*
+** div_1_f64_m_untied:
+**	fmov	(z[0-9]+\.d), #1.0(e\+0)?
+**	movprfx	z0, z1
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f64_m_untied, svfloat64_t,
+		z0 = svdiv_n_f64_m (p0, z1, 1),
+		z0 = svdiv_m (p0, z1, 1))
+
+/*
+** div_f64_z_tied1:
+**	movprfx	z0\.d, p0/z, z0\.d
+**	fdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_f64_z_tied1, svfloat64_t,
+		z0 = svdiv_f64_z (p0, z0, z1),
+		z0 = svdiv_z (p0, z0, z1))
+
+/*
+** div_f64_z_tied2:
+**	movprfx	z1\.d, p0/z, z1\.d
+**	fdivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_f64_z_tied2, svfloat64_t,
+		z1 = svdiv_f64_z (p0, z0, z1),
+		z1 = svdiv_z (p0, z0, z1))
+
+/*
+** div_f64_z_untied:
+**	movprfx	z0\.d, p0/z, z1\.d
+**	fdiv	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_f64_z_untied, svfloat64_t,
+		z0 = svdiv_f64_z (p0, z1, z2),
+		z0 = svdiv_z (p0, z1, z2))
+
+/*
+** div_x0_f64_z_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z0\.d
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_f64_z_tied1, svfloat64_t, double,
+		 z0 = svdiv_n_f64_z (p0, z0, x0),
+		 z0 = svdiv_z (p0, z0, x0))
+
+/*
+** div_x0_f64_z_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z1\.d
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_f64_z_untied, svfloat64_t, double,
+		 z0 = svdiv_n_f64_z (p0, z1, x0),
+		 z0 = svdiv_z (p0, z1, x0))
+
+/*
+** div_d0_f64_z_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z1\.d
+**	fdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_f64_z_tied1, svfloat64_t, double,
+		 z1 = svdiv_n_f64_z (p0, z1, d0),
+		 z1 = svdiv_z (p0, z1, d0))
+
+/*
+** div_d0_f64_z_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z2\.d
+**	fdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_f64_z_untied, svfloat64_t, double,
+		 z1 = svdiv_n_f64_z (p0, z2, d0),
+		 z1 = svdiv_z (p0, z2, d0))
+
+/*
+** div_1_f64_z_tied1:
+**	fmov	(z[0-9]+\.d), #1.0(e\+0)?
+**	movprfx	z0\.d, p0/z, z0\.d
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f64_z_tied1, svfloat64_t,
+		z0 = svdiv_n_f64_z (p0, z0, 1),
+		z0 = svdiv_z (p0, z0, 1))
+
+/*
+** div_1_f64_z_untied:
+**	fmov	(z[0-9]+\.d), #1.0(e\+0)?
+**	movprfx	z1\.d, p0/z, z0\.d
+**	fdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f64_z_untied, svfloat64_t,
+		z1 = svdiv_n_f64_z (p0, z0, 1),
+		z1 = svdiv_z (p0, z0, 1))
+
+/*
+** div_0p5_f64_z_untied:
+**	fmov	(z[0-9]+\.d), #5.0(e\-1)?
+**	movprfx	z0\.d, p0/z, z1\.d
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_0p5_f64_z_untied, svfloat64_t,
+		z0 = svdiv_n_f64_z (p0, z1, 0.5),
+		z0 = svdiv_z (p0, z1, 0.5))
+
+/*
+** div_f64_x_tied1:
+**	fdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_f64_x_tied1, svfloat64_t,
+		z0 = svdiv_f64_x (p0, z0, z1),
+		z0 = svdiv_x (p0, z0, z1))
+
+/*
+** div_f64_x_tied2:
+**	fdivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_f64_x_tied2, svfloat64_t,
+		z1 = svdiv_f64_x (p0, z0, z1),
+		z1 = svdiv_x (p0, z0, z1))
+
+/*
+** div_f64_x_untied:
+**	movprfx	z2, z0
+**	fdiv	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_f64_x_untied, svfloat64_t,
+		z2 = svdiv_f64_x (p0, z0, z1),
+		z2 = svdiv_x (p0, z0, z1))
+
+/*
+** div_x0_f64_x_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_f64_x_tied1, svfloat64_t, double,
+		 z0 = svdiv_n_f64_x (p0, z0, x0),
+		 z0 = svdiv_x (p0, z0, x0))
+
+/*
+** div_x0_f64_x_untied:
+**	mov	z1\.d, x0
+**	fdivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_f64_x_untied, svfloat64_t, double,
+		 z1 = svdiv_n_f64_x (p0, z0, x0),
+		 z1 = svdiv_x (p0, z0, x0))
+
+/*
+** div_d0_f64_x_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	fdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_f64_x_tied1, svfloat64_t, double,
+		 z1 = svdiv_n_f64_x (p0, z1, d0),
+		 z1 = svdiv_x (p0, z1, d0))
+
+/*
+** div_d0_f64_x_untied:
+**	mov	z2\.d, d0
+**	fdivr	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_f64_x_untied, svfloat64_t, double,
+		 z2 = svdiv_n_f64_x (p0, z1, d0),
+		 z2 = svdiv_x (p0, z1, d0))
+
+/*
+** div_1_f64_x_tied1:
+**	fmov	(z[0-9]+\.d), #1\.0(e\+0)?
+**	fdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f64_x_tied1, svfloat64_t,
+		z0 = svdiv_n_f64_x (p0, z0, 1),
+		z0 = svdiv_x (p0, z0, 1))
+
+/*
+** div_1_f64_x_untied:
+**	fmov	z0\.d, #1\.0(e\+0)?
+**	fdivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_1_f64_x_untied, svfloat64_t,
+		z0 = svdiv_n_f64_x (p0, z1, 1),
+		z0 = svdiv_x (p0, z1, 1))
+
+/*
+** ptrue_div_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fdiv	z0\.d, \1/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f64_x_tied1, svfloat64_t,
+		z0 = svdiv_f64_x (svptrue_b64 (), z0, z1),
+		z0 = svdiv_x (svptrue_b64 (), z0, z1))
+
+/*
+** ptrue_div_f64_x_tied2:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fdivr	z1\.d, \1/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f64_x_tied2, svfloat64_t,
+		z1 = svdiv_f64_x (svptrue_b64 (), z0, z1),
+		z1 = svdiv_x (svptrue_b64 (), z0, z1))
+
+/*
+** ptrue_div_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	movprfx	z2, z0
+**	fdiv	z2\.d, \1/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_f64_x_untied, svfloat64_t,
+		z2 = svdiv_f64_x (svptrue_b64 (), z0, z1),
+		z2 = svdiv_x (svptrue_b64 (), z0, z1))
+
+/*
+** ptrue_div_x0_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	mov	(z[0-9]+\.d), x0
+**	fdiv	z0\.d, \1/m, z0\.d, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_x0_f64_x_tied1, svfloat64_t, double,
+		 z0 = svdiv_n_f64_x (svptrue_b64 (), z0, x0),
+		 z0 = svdiv_x (svptrue_b64 (), z0, x0))
+
+/*
+** ptrue_div_x0_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	mov	z1\.d, x0
+**	fdivr	z1\.d, \1/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_x0_f64_x_untied, svfloat64_t, double,
+		 z1 = svdiv_n_f64_x (svptrue_b64 (), z0, x0),
+		 z1 = svdiv_x (svptrue_b64 (), z0, x0))
+
+/*
+** ptrue_div_d0_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	mov	(z[0-9]+\.d), d0
+**	fdiv	z1\.d, \1/m, z1\.d, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_d0_f64_x_tied1, svfloat64_t, double,
+		 z1 = svdiv_n_f64_x (svptrue_b64 (), z1, d0),
+		 z1 = svdiv_x (svptrue_b64 (), z1, d0))
+
+/*
+** ptrue_div_d0_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	mov	z2\.d, d0
+**	fdivr	z2\.d, \1/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_div_d0_f64_x_untied, svfloat64_t, double,
+		 z2 = svdiv_n_f64_x (svptrue_b64 (), z1, d0),
+		 z2 = svdiv_x (svptrue_b64 (), z1, d0))
+
+/*
+** ptrue_div_1_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fmov	z0\.d, #1.0(e\+0)?
+**	fdivr	z0\.d, \1/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_1_f64_x_untied, svfloat64_t,
+		z0 = svdiv_n_f64_x (svptrue_b64 (), z1, 1),
+		z0 = svdiv_x (svptrue_b64 (), z1, 1))
+
+/*
+** ptrue_div_1_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fmov	(z[0-9]+\.d), #1.0(e\+0)?
+**	fdiv	z1\.d, \1/m, z1\.d, \2
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_div_1_f64_x_tied1, svfloat64_t,
+		z1 = svdiv_n_f64_x (svptrue_b64 (), z1, 1),
+		z1 = svdiv_x (svptrue_b64 (), z1, 1))
+
+/*
+** ptrue_b8_div_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fdiv	z0\.d, \1/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f64_x_tied1, svfloat64_t,
+		z0 = svdiv_f64_x (svptrue_b8 (), z0, z1),
+		z0 = svdiv_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_div_f64_x_tied2:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fdivr	z1\.d, \1/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f64_x_tied2, svfloat64_t,
+		z1 = svdiv_f64_x (svptrue_b8 (), z0, z1),
+		z1 = svdiv_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_div_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	movprfx	z2, z0
+**	fdiv	z2\.d, \1/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_div_f64_x_untied, svfloat64_t,
+		z2 = svdiv_f64_x (svptrue_b8 (), z0, z1),
+		z2 = svdiv_x (svptrue_b8 (), z0, z1))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_s32.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_s32.c
new file mode 100644
index 0000000..8c841ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_s32.c
@@ -0,0 +1,254 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** div_s32_m_tied1:
+**	sdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_s32_m_tied1, svint32_t,
+		z0 = svdiv_s32_m (p0, z0, z1),
+		z0 = svdiv_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (div_s32_m_tied2, svint32_t,
+		z1 = svdiv_s32_m (p0, z0, z1),
+		z1 = svdiv_m (p0, z0, z1))
+
+/*
+** div_s32_m_untied:
+**	movprfx	z0, z1
+**	sdiv	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_s32_m_untied, svint32_t,
+		z0 = svdiv_s32_m (p0, z1, z2),
+		z0 = svdiv_m (p0, z1, z2))
+
+/*
+** div_w0_s32_m_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	sdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_s32_m_tied1, svint32_t, int32_t,
+		 z0 = svdiv_n_s32_m (p0, z0, x0),
+		 z0 = svdiv_m (p0, z0, x0))
+
+/*
+** div_w0_s32_m_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0, z1
+**	sdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_s32_m_untied, svint32_t, int32_t,
+		 z0 = svdiv_n_s32_m (p0, z1, x0),
+		 z0 = svdiv_m (p0, z1, x0))
+
+/*
+** div_s0_s32_m_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	sdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_s32_m_tied1, svint32_t, int32_t,
+		 z1 = svdiv_n_s32_m (p0, z1, d0),
+		 z1 = svdiv_m (p0, z1, d0))
+
+/*
+** div_s0_s32_m_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1, z2
+**	sdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_s32_m_untied, svint32_t, int32_t,
+		 z1 = svdiv_n_s32_m (p0, z2, d0),
+		 z1 = svdiv_m (p0, z2, d0))
+
+/*
+** div_2_s32_m_tied1:
+**	mov	(z[0-9]+\.s), #2
+**	sdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_s32_m_tied1, svint32_t,
+		z0 = svdiv_n_s32_m (p0, z0, 2),
+		z0 = svdiv_m (p0, z0, 2))
+
+/*
+** div_2_s32_m_untied:
+**	mov	(z[0-9]+\.s), #2
+**	movprfx	z0, z1
+**	sdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_s32_m_untied, svint32_t,
+		z0 = svdiv_n_s32_m (p0, z1, 2),
+		z0 = svdiv_m (p0, z1, 2))
+
+/*
+** div_s32_z_tied1:
+**	movprfx	z0\.s, p0/z, z0\.s
+**	sdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_s32_z_tied1, svint32_t,
+		z0 = svdiv_s32_z (p0, z0, z1),
+		z0 = svdiv_z (p0, z0, z1))
+
+/*
+** div_s32_z_tied2:
+**	movprfx	z1\.s, p0/z, z1\.s
+**	sdivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_s32_z_tied2, svint32_t,
+		z1 = svdiv_s32_z (p0, z0, z1),
+		z1 = svdiv_z (p0, z0, z1))
+
+/*
+** div_s32_z_untied:
+**	movprfx	z0\.s, p0/z, z1\.s
+**	sdiv	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_s32_z_untied, svint32_t,
+		z0 = svdiv_s32_z (p0, z1, z2),
+		z0 = svdiv_z (p0, z1, z2))
+
+/*
+** div_w0_s32_z_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z0\.s
+**	sdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_s32_z_tied1, svint32_t, int32_t,
+		 z0 = svdiv_n_s32_z (p0, z0, x0),
+		 z0 = svdiv_z (p0, z0, x0))
+
+/*
+** div_w0_s32_z_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z1\.s
+**	sdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_s32_z_untied, svint32_t, int32_t,
+		 z0 = svdiv_n_s32_z (p0, z1, x0),
+		 z0 = svdiv_z (p0, z1, x0))
+
+/*
+** div_s0_s32_z_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z1\.s
+**	sdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_s32_z_tied1, svint32_t, int32_t,
+		 z1 = svdiv_n_s32_z (p0, z1, d0),
+		 z1 = svdiv_z (p0, z1, d0))
+
+/*
+** div_s0_s32_z_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z2\.s
+**	sdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_s32_z_untied, svint32_t, int32_t,
+		 z1 = svdiv_n_s32_z (p0, z2, d0),
+		 z1 = svdiv_z (p0, z2, d0))
+
+/*
+** div_s32_x_tied1:
+**	sdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_s32_x_tied1, svint32_t,
+		z0 = svdiv_s32_x (p0, z0, z1),
+		z0 = svdiv_x (p0, z0, z1))
+
+/*
+** div_s32_x_tied2:
+**	sdivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_s32_x_tied2, svint32_t,
+		z1 = svdiv_s32_x (p0, z0, z1),
+		z1 = svdiv_x (p0, z0, z1))
+
+/*
+** div_s32_x_untied:
+**	movprfx	z2, z0
+**	sdiv	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_s32_x_untied, svint32_t,
+		z2 = svdiv_s32_x (p0, z0, z1),
+		z2 = svdiv_x (p0, z0, z1))
+
+/*
+** div_w0_s32_x_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	sdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_s32_x_tied1, svint32_t, int32_t,
+		 z0 = svdiv_n_s32_x (p0, z0, x0),
+		 z0 = svdiv_x (p0, z0, x0))
+
+/*
+** div_w0_s32_x_untied:
+**	mov	z1\.s, w0
+**	sdivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_s32_x_untied, svint32_t, int32_t,
+		 z1 = svdiv_n_s32_x (p0, z0, x0),
+		 z1 = svdiv_x (p0, z0, x0))
+
+/*
+** div_s0_s32_x_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	sdiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_s32_x_tied1, svint32_t, int32_t,
+		 z1 = svdiv_n_s32_x (p0, z1, d0),
+		 z1 = svdiv_x (p0, z1, d0))
+
+/*
+** div_s0_s32_x_untied:
+**	mov	z2\.s, s0
+**	sdivr	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_s32_x_untied, svint32_t, int32_t,
+		 z2 = svdiv_n_s32_x (p0, z1, d0),
+		 z2 = svdiv_x (p0, z1, d0))
+
+/*
+** div_2_s32_x_tied1:
+**	mov	(z[0-9]+\.s), #2
+**	sdiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_s32_x_tied1, svint32_t,
+		z0 = svdiv_n_s32_x (p0, z0, 2),
+		z0 = svdiv_x (p0, z0, 2))
+
+/*
+** div_2_s32_x_untied:
+**	mov	z0\.s, #2
+**	sdivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_s32_x_untied, svint32_t,
+		z0 = svdiv_n_s32_x (p0, z1, 2),
+		z0 = svdiv_x (p0, z1, 2))
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_s64.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_s64.c
new file mode 100644
index 0000000..8cc2b31
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_s64.c
@@ -0,0 +1,254 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** div_s64_m_tied1:
+**	sdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_s64_m_tied1, svint64_t,
+		z0 = svdiv_s64_m (p0, z0, z1),
+		z0 = svdiv_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (div_s64_m_tied2, svint64_t,
+		z1 = svdiv_s64_m (p0, z0, z1),
+		z1 = svdiv_m (p0, z0, z1))
+
+/*
+** div_s64_m_untied:
+**	movprfx	z0, z1
+**	sdiv	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_s64_m_untied, svint64_t,
+		z0 = svdiv_s64_m (p0, z1, z2),
+		z0 = svdiv_m (p0, z1, z2))
+
+/*
+** div_x0_s64_m_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	sdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_s64_m_tied1, svint64_t, int64_t,
+		 z0 = svdiv_n_s64_m (p0, z0, x0),
+		 z0 = svdiv_m (p0, z0, x0))
+
+/*
+** div_x0_s64_m_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0, z1
+**	sdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_s64_m_untied, svint64_t, int64_t,
+		 z0 = svdiv_n_s64_m (p0, z1, x0),
+		 z0 = svdiv_m (p0, z1, x0))
+
+/*
+** div_d0_s64_m_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	sdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_s64_m_tied1, svint64_t, int64_t,
+		 z1 = svdiv_n_s64_m (p0, z1, d0),
+		 z1 = svdiv_m (p0, z1, d0))
+
+/*
+** div_d0_s64_m_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1, z2
+**	sdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_s64_m_untied, svint64_t, int64_t,
+		 z1 = svdiv_n_s64_m (p0, z2, d0),
+		 z1 = svdiv_m (p0, z2, d0))
+
+/*
+** div_2_s64_m_tied1:
+**	mov	(z[0-9]+\.d), #2
+**	sdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_s64_m_tied1, svint64_t,
+		z0 = svdiv_n_s64_m (p0, z0, 2),
+		z0 = svdiv_m (p0, z0, 2))
+
+/*
+** div_2_s64_m_untied:
+**	mov	(z[0-9]+\.d), #2
+**	movprfx	z0, z1
+**	sdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_s64_m_untied, svint64_t,
+		z0 = svdiv_n_s64_m (p0, z1, 2),
+		z0 = svdiv_m (p0, z1, 2))
+
+/*
+** div_s64_z_tied1:
+**	movprfx	z0\.d, p0/z, z0\.d
+**	sdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_s64_z_tied1, svint64_t,
+		z0 = svdiv_s64_z (p0, z0, z1),
+		z0 = svdiv_z (p0, z0, z1))
+
+/*
+** div_s64_z_tied2:
+**	movprfx	z1\.d, p0/z, z1\.d
+**	sdivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_s64_z_tied2, svint64_t,
+		z1 = svdiv_s64_z (p0, z0, z1),
+		z1 = svdiv_z (p0, z0, z1))
+
+/*
+** div_s64_z_untied:
+**	movprfx	z0\.d, p0/z, z1\.d
+**	sdiv	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_s64_z_untied, svint64_t,
+		z0 = svdiv_s64_z (p0, z1, z2),
+		z0 = svdiv_z (p0, z1, z2))
+
+/*
+** div_x0_s64_z_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z0\.d
+**	sdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_s64_z_tied1, svint64_t, int64_t,
+		 z0 = svdiv_n_s64_z (p0, z0, x0),
+		 z0 = svdiv_z (p0, z0, x0))
+
+/*
+** div_x0_s64_z_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z1\.d
+**	sdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_s64_z_untied, svint64_t, int64_t,
+		 z0 = svdiv_n_s64_z (p0, z1, x0),
+		 z0 = svdiv_z (p0, z1, x0))
+
+/*
+** div_d0_s64_z_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z1\.d
+**	sdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_s64_z_tied1, svint64_t, int64_t,
+		 z1 = svdiv_n_s64_z (p0, z1, d0),
+		 z1 = svdiv_z (p0, z1, d0))
+
+/*
+** div_d0_s64_z_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z2\.d
+**	sdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_s64_z_untied, svint64_t, int64_t,
+		 z1 = svdiv_n_s64_z (p0, z2, d0),
+		 z1 = svdiv_z (p0, z2, d0))
+
+/*
+** div_s64_x_tied1:
+**	sdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_s64_x_tied1, svint64_t,
+		z0 = svdiv_s64_x (p0, z0, z1),
+		z0 = svdiv_x (p0, z0, z1))
+
+/*
+** div_s64_x_tied2:
+**	sdivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_s64_x_tied2, svint64_t,
+		z1 = svdiv_s64_x (p0, z0, z1),
+		z1 = svdiv_x (p0, z0, z1))
+
+/*
+** div_s64_x_untied:
+**	movprfx	z2, z0
+**	sdiv	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_s64_x_untied, svint64_t,
+		z2 = svdiv_s64_x (p0, z0, z1),
+		z2 = svdiv_x (p0, z0, z1))
+
+/*
+** div_x0_s64_x_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	sdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_s64_x_tied1, svint64_t, int64_t,
+		 z0 = svdiv_n_s64_x (p0, z0, x0),
+		 z0 = svdiv_x (p0, z0, x0))
+
+/*
+** div_x0_s64_x_untied:
+**	mov	z1\.d, x0
+**	sdivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_s64_x_untied, svint64_t, int64_t,
+		 z1 = svdiv_n_s64_x (p0, z0, x0),
+		 z1 = svdiv_x (p0, z0, x0))
+
+/*
+** div_d0_s64_x_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	sdiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_s64_x_tied1, svint64_t, int64_t,
+		 z1 = svdiv_n_s64_x (p0, z1, d0),
+		 z1 = svdiv_x (p0, z1, d0))
+
+/*
+** div_d0_s64_x_untied:
+**	mov	z2\.d, d0
+**	sdivr	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_s64_x_untied, svint64_t, int64_t,
+		 z2 = svdiv_n_s64_x (p0, z1, d0),
+		 z2 = svdiv_x (p0, z1, d0))
+
+/*
+** div_2_s64_x_tied1:
+**	mov	(z[0-9]+\.d), #2
+**	sdiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_s64_x_tied1, svint64_t,
+		z0 = svdiv_n_s64_x (p0, z0, 2),
+		z0 = svdiv_x (p0, z0, 2))
+
+/*
+** div_2_s64_x_untied:
+**	mov	z0\.d, #2
+**	sdivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_s64_x_untied, svint64_t,
+		z0 = svdiv_n_s64_x (p0, z1, 2),
+		z0 = svdiv_x (p0, z1, 2))
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_u32.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_u32.c
new file mode 100644
index 0000000..94f34eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_u32.c
@@ -0,0 +1,254 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** div_u32_m_tied1:
+**	udiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_u32_m_tied1, svuint32_t,
+		z0 = svdiv_u32_m (p0, z0, z1),
+		z0 = svdiv_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (div_u32_m_tied2, svuint32_t,
+		z1 = svdiv_u32_m (p0, z0, z1),
+		z1 = svdiv_m (p0, z0, z1))
+
+/*
+** div_u32_m_untied:
+**	movprfx	z0, z1
+**	udiv	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_u32_m_untied, svuint32_t,
+		z0 = svdiv_u32_m (p0, z1, z2),
+		z0 = svdiv_m (p0, z1, z2))
+
+/*
+** div_w0_u32_m_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	udiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_u32_m_tied1, svuint32_t, uint32_t,
+		 z0 = svdiv_n_u32_m (p0, z0, x0),
+		 z0 = svdiv_m (p0, z0, x0))
+
+/*
+** div_w0_u32_m_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0, z1
+**	udiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_u32_m_untied, svuint32_t, uint32_t,
+		 z0 = svdiv_n_u32_m (p0, z1, x0),
+		 z0 = svdiv_m (p0, z1, x0))
+
+/*
+** div_s0_u32_m_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	udiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_u32_m_tied1, svuint32_t, uint32_t,
+		 z1 = svdiv_n_u32_m (p0, z1, d0),
+		 z1 = svdiv_m (p0, z1, d0))
+
+/*
+** div_s0_u32_m_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1, z2
+**	udiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_u32_m_untied, svuint32_t, uint32_t,
+		 z1 = svdiv_n_u32_m (p0, z2, d0),
+		 z1 = svdiv_m (p0, z2, d0))
+
+/*
+** div_2_u32_m_tied1:
+**	mov	(z[0-9]+\.s), #2
+**	udiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_u32_m_tied1, svuint32_t,
+		z0 = svdiv_n_u32_m (p0, z0, 2),
+		z0 = svdiv_m (p0, z0, 2))
+
+/*
+** div_2_u32_m_untied:
+**	mov	(z[0-9]+\.s), #2
+**	movprfx	z0, z1
+**	udiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_u32_m_untied, svuint32_t,
+		z0 = svdiv_n_u32_m (p0, z1, 2),
+		z0 = svdiv_m (p0, z1, 2))
+
+/*
+** div_u32_z_tied1:
+**	movprfx	z0\.s, p0/z, z0\.s
+**	udiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_u32_z_tied1, svuint32_t,
+		z0 = svdiv_u32_z (p0, z0, z1),
+		z0 = svdiv_z (p0, z0, z1))
+
+/*
+** div_u32_z_tied2:
+**	movprfx	z1\.s, p0/z, z1\.s
+**	udivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_u32_z_tied2, svuint32_t,
+		z1 = svdiv_u32_z (p0, z0, z1),
+		z1 = svdiv_z (p0, z0, z1))
+
+/*
+** div_u32_z_untied:
+**	movprfx	z0\.s, p0/z, z1\.s
+**	udiv	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_u32_z_untied, svuint32_t,
+		z0 = svdiv_u32_z (p0, z1, z2),
+		z0 = svdiv_z (p0, z1, z2))
+
+/*
+** div_w0_u32_z_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z0\.s
+**	udiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_u32_z_tied1, svuint32_t, uint32_t,
+		 z0 = svdiv_n_u32_z (p0, z0, x0),
+		 z0 = svdiv_z (p0, z0, x0))
+
+/*
+** div_w0_u32_z_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z1\.s
+**	udiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_u32_z_untied, svuint32_t, uint32_t,
+		 z0 = svdiv_n_u32_z (p0, z1, x0),
+		 z0 = svdiv_z (p0, z1, x0))
+
+/*
+** div_s0_u32_z_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z1\.s
+**	udiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_u32_z_tied1, svuint32_t, uint32_t,
+		 z1 = svdiv_n_u32_z (p0, z1, d0),
+		 z1 = svdiv_z (p0, z1, d0))
+
+/*
+** div_s0_u32_z_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z2\.s
+**	udiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_u32_z_untied, svuint32_t, uint32_t,
+		 z1 = svdiv_n_u32_z (p0, z2, d0),
+		 z1 = svdiv_z (p0, z2, d0))
+
+/*
+** div_u32_x_tied1:
+**	udiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_u32_x_tied1, svuint32_t,
+		z0 = svdiv_u32_x (p0, z0, z1),
+		z0 = svdiv_x (p0, z0, z1))
+
+/*
+** div_u32_x_tied2:
+**	udivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_u32_x_tied2, svuint32_t,
+		z1 = svdiv_u32_x (p0, z0, z1),
+		z1 = svdiv_x (p0, z0, z1))
+
+/*
+** div_u32_x_untied:
+**	movprfx	z2, z0
+**	udiv	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_u32_x_untied, svuint32_t,
+		z2 = svdiv_u32_x (p0, z0, z1),
+		z2 = svdiv_x (p0, z0, z1))
+
+/*
+** div_w0_u32_x_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	udiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_u32_x_tied1, svuint32_t, uint32_t,
+		 z0 = svdiv_n_u32_x (p0, z0, x0),
+		 z0 = svdiv_x (p0, z0, x0))
+
+/*
+** div_w0_u32_x_untied:
+**	mov	z1\.s, w0
+**	udivr	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (div_w0_u32_x_untied, svuint32_t, uint32_t,
+		 z1 = svdiv_n_u32_x (p0, z0, x0),
+		 z1 = svdiv_x (p0, z0, x0))
+
+/*
+** div_s0_u32_x_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	udiv	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_u32_x_tied1, svuint32_t, uint32_t,
+		 z1 = svdiv_n_u32_x (p0, z1, d0),
+		 z1 = svdiv_x (p0, z1, d0))
+
+/*
+** div_s0_u32_x_untied:
+**	mov	z2\.s, s0
+**	udivr	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (div_s0_u32_x_untied, svuint32_t, uint32_t,
+		 z2 = svdiv_n_u32_x (p0, z1, d0),
+		 z2 = svdiv_x (p0, z1, d0))
+
+/*
+** div_2_u32_x_tied1:
+**	mov	(z[0-9]+\.s), #2
+**	udiv	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_u32_x_tied1, svuint32_t,
+		z0 = svdiv_n_u32_x (p0, z0, 2),
+		z0 = svdiv_x (p0, z0, 2))
+
+/*
+** div_2_u32_x_untied:
+**	mov	z0\.s, #2
+**	udivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_u32_x_untied, svuint32_t,
+		z0 = svdiv_n_u32_x (p0, z1, 2),
+		z0 = svdiv_x (p0, z1, 2))
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_u64.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_u64.c
new file mode 100644
index 0000000..d329068
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/div_u64.c
@@ -0,0 +1,254 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** div_u64_m_tied1:
+**	udiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_u64_m_tied1, svuint64_t,
+		z0 = svdiv_u64_m (p0, z0, z1),
+		z0 = svdiv_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (div_u64_m_tied2, svuint64_t,
+		z1 = svdiv_u64_m (p0, z0, z1),
+		z1 = svdiv_m (p0, z0, z1))
+
+/*
+** div_u64_m_untied:
+**	movprfx	z0, z1
+**	udiv	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_u64_m_untied, svuint64_t,
+		z0 = svdiv_u64_m (p0, z1, z2),
+		z0 = svdiv_m (p0, z1, z2))
+
+/*
+** div_x0_u64_m_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	udiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_u64_m_tied1, svuint64_t, uint64_t,
+		 z0 = svdiv_n_u64_m (p0, z0, x0),
+		 z0 = svdiv_m (p0, z0, x0))
+
+/*
+** div_x0_u64_m_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0, z1
+**	udiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_u64_m_untied, svuint64_t, uint64_t,
+		 z0 = svdiv_n_u64_m (p0, z1, x0),
+		 z0 = svdiv_m (p0, z1, x0))
+
+/*
+** div_d0_u64_m_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	udiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_u64_m_tied1, svuint64_t, uint64_t,
+		 z1 = svdiv_n_u64_m (p0, z1, d0),
+		 z1 = svdiv_m (p0, z1, d0))
+
+/*
+** div_d0_u64_m_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1, z2
+**	udiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_u64_m_untied, svuint64_t, uint64_t,
+		 z1 = svdiv_n_u64_m (p0, z2, d0),
+		 z1 = svdiv_m (p0, z2, d0))
+
+/*
+** div_2_u64_m_tied1:
+**	mov	(z[0-9]+\.d), #2
+**	udiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_u64_m_tied1, svuint64_t,
+		z0 = svdiv_n_u64_m (p0, z0, 2),
+		z0 = svdiv_m (p0, z0, 2))
+
+/*
+** div_2_u64_m_untied:
+**	mov	(z[0-9]+\.d), #2
+**	movprfx	z0, z1
+**	udiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_u64_m_untied, svuint64_t,
+		z0 = svdiv_n_u64_m (p0, z1, 2),
+		z0 = svdiv_m (p0, z1, 2))
+
+/*
+** div_u64_z_tied1:
+**	movprfx	z0\.d, p0/z, z0\.d
+**	udiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_u64_z_tied1, svuint64_t,
+		z0 = svdiv_u64_z (p0, z0, z1),
+		z0 = svdiv_z (p0, z0, z1))
+
+/*
+** div_u64_z_tied2:
+**	movprfx	z1\.d, p0/z, z1\.d
+**	udivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_u64_z_tied2, svuint64_t,
+		z1 = svdiv_u64_z (p0, z0, z1),
+		z1 = svdiv_z (p0, z0, z1))
+
+/*
+** div_u64_z_untied:
+**	movprfx	z0\.d, p0/z, z1\.d
+**	udiv	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_u64_z_untied, svuint64_t,
+		z0 = svdiv_u64_z (p0, z1, z2),
+		z0 = svdiv_z (p0, z1, z2))
+
+/*
+** div_x0_u64_z_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z0\.d
+**	udiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_u64_z_tied1, svuint64_t, uint64_t,
+		 z0 = svdiv_n_u64_z (p0, z0, x0),
+		 z0 = svdiv_z (p0, z0, x0))
+
+/*
+** div_x0_u64_z_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z1\.d
+**	udiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_u64_z_untied, svuint64_t, uint64_t,
+		 z0 = svdiv_n_u64_z (p0, z1, x0),
+		 z0 = svdiv_z (p0, z1, x0))
+
+/*
+** div_d0_u64_z_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z1\.d
+**	udiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_u64_z_tied1, svuint64_t, uint64_t,
+		 z1 = svdiv_n_u64_z (p0, z1, d0),
+		 z1 = svdiv_z (p0, z1, d0))
+
+/*
+** div_d0_u64_z_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z2\.d
+**	udiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_u64_z_untied, svuint64_t, uint64_t,
+		 z1 = svdiv_n_u64_z (p0, z2, d0),
+		 z1 = svdiv_z (p0, z2, d0))
+
+/*
+** div_u64_x_tied1:
+**	udiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_u64_x_tied1, svuint64_t,
+		z0 = svdiv_u64_x (p0, z0, z1),
+		z0 = svdiv_x (p0, z0, z1))
+
+/*
+** div_u64_x_tied2:
+**	udivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_u64_x_tied2, svuint64_t,
+		z1 = svdiv_u64_x (p0, z0, z1),
+		z1 = svdiv_x (p0, z0, z1))
+
+/*
+** div_u64_x_untied:
+**	movprfx	z2, z0
+**	udiv	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_u64_x_untied, svuint64_t,
+		z2 = svdiv_u64_x (p0, z0, z1),
+		z2 = svdiv_x (p0, z0, z1))
+
+/*
+** div_x0_u64_x_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	udiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_u64_x_tied1, svuint64_t, uint64_t,
+		 z0 = svdiv_n_u64_x (p0, z0, x0),
+		 z0 = svdiv_x (p0, z0, x0))
+
+/*
+** div_x0_u64_x_untied:
+**	mov	z1\.d, x0
+**	udivr	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (div_x0_u64_x_untied, svuint64_t, uint64_t,
+		 z1 = svdiv_n_u64_x (p0, z0, x0),
+		 z1 = svdiv_x (p0, z0, x0))
+
+/*
+** div_d0_u64_x_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	udiv	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_u64_x_tied1, svuint64_t, uint64_t,
+		 z1 = svdiv_n_u64_x (p0, z1, d0),
+		 z1 = svdiv_x (p0, z1, d0))
+
+/*
+** div_d0_u64_x_untied:
+**	mov	z2\.d, d0
+**	udivr	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (div_d0_u64_x_untied, svuint64_t, uint64_t,
+		 z2 = svdiv_n_u64_x (p0, z1, d0),
+		 z2 = svdiv_x (p0, z1, d0))
+
+/*
+** div_2_u64_x_tied1:
+**	mov	(z[0-9]+\.d), #2
+**	udiv	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_u64_x_tied1, svuint64_t,
+		z0 = svdiv_n_u64_x (p0, z0, 2),
+		z0 = svdiv_x (p0, z0, 2))
+
+/*
+** div_2_u64_x_untied:
+**	mov	z0\.d, #2
+**	udivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (div_2_u64_x_untied, svuint64_t,
+		z0 = svdiv_n_u64_x (p0, z1, 2),
+		z0 = svdiv_x (p0, z1, 2))
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f16.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f16.c
new file mode 100644
index 0000000..bd01564
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f16.c
@@ -0,0 +1,425 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** divr_f16_m_tied1:
+**	fdivr	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f16_m_tied1, svfloat16_t,
+		z0 = svdivr_f16_m (p0, z0, z1),
+		z0 = svdivr_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (divr_f16_m_tied2, svfloat16_t,
+		z1 = svdivr_f16_m (p0, z0, z1),
+		z1 = svdivr_m (p0, z0, z1))
+
+/*
+** divr_f16_m_untied:
+**	movprfx	z0, z1
+**	fdivr	z0\.h, p0/m, z0\.h, z2\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f16_m_untied, svfloat16_t,
+		z0 = svdivr_f16_m (p0, z1, z2),
+		z0 = svdivr_m (p0, z1, z2))
+
+/*
+** divr_w0_f16_m_tied1:
+**	mov	(z[0-9]+\.h), w0
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f16_m_tied1, svfloat16_t, __fp16,
+		 z0 = svdivr_n_f16_m (p0, z0, x0),
+		 z0 = svdivr_m (p0, z0, x0))
+
+/*
+** divr_w0_f16_m_untied:
+**	mov	(z[0-9]+\.h), w0
+**	movprfx	z0, z1
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f16_m_untied, svfloat16_t, __fp16,
+		 z0 = svdivr_n_f16_m (p0, z1, x0),
+		 z0 = svdivr_m (p0, z1, x0))
+
+/*
+** divr_h0_f16_m_tied1:
+**	mov	(z[0-9]+\.h), h0
+**	fdivr	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_h0_f16_m_tied1, svfloat16_t, __fp16,
+		 z1 = svdivr_n_f16_m (p0, z1, d0),
+		 z1 = svdivr_m (p0, z1, d0))
+
+/*
+** divr_h0_f16_m_untied:
+**	mov	(z[0-9]+\.h), h0
+**	movprfx	z1, z2
+**	fdivr	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_h0_f16_m_untied, svfloat16_t, __fp16,
+		 z1 = svdivr_n_f16_m (p0, z2, d0),
+		 z1 = svdivr_m (p0, z2, d0))
+
+/*
+** divr_1_f16_m_tied1:
+**	fmov	(z[0-9]+\.h), #1.0(e\+0)?
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f16_m_tied1, svfloat16_t,
+		z0 = svdivr_n_f16_m (p0, z0, 1),
+		z0 = svdivr_m (p0, z0, 1))
+
+/*
+** divr_1_f16_m_untied:
+**	fmov	(z[0-9]+\.h), #1.0(e\+0)?
+**	movprfx	z0, z1
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f16_m_untied, svfloat16_t,
+		z0 = svdivr_n_f16_m (p0, z1, 1),
+		z0 = svdivr_m (p0, z1, 1))
+
+/*
+** divr_0p5_f16_m_tied1:
+**	fmov	(z[0-9]+\.h), #5.0(e\-1)?
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f16_m_tied1, svfloat16_t,
+		z0 = svdivr_n_f16_m (p0, z0, 0.5),
+		z0 = svdivr_m (p0, z0, 0.5))
+
+/*
+** divr_0p5_f16_m_untied:
+**	fmov	(z[0-9]+\.h), #5.0(e\-1)?
+**	movprfx	z0, z1
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f16_m_untied, svfloat16_t,
+		z0 = svdivr_n_f16_m (p0, z1, 0.5),
+		z0 = svdivr_m (p0, z1, 0.5))
+
+
+/*
+** divr_f16_z_tied1:
+**	movprfx	z0\.h, p0/z, z0\.h
+**	fdivr	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f16_z_tied1, svfloat16_t,
+		z0 = svdivr_f16_z (p0, z0, z1),
+		z0 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_f16_z_tied2:
+**	movprfx	z1\.h, p0/z, z1\.h
+**	fdiv	z1\.h, p0/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f16_z_tied2, svfloat16_t,
+		z1 = svdivr_f16_z (p0, z0, z1),
+		z1 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_f16_z_untied:
+**	movprfx	z0\.h, p0/z, z2\.h
+**	fdiv	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f16_z_untied, svfloat16_t,
+		z0 = svdivr_f16_z (p0, z1, z2),
+		z0 = svdivr_z (p0, z1, z2))
+
+/*
+** divr_w0_f16_z_tied1:
+**	mov	(z[0-9]+\.h), w0
+**	movprfx	z0\.h, p0/z, z0\.h
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f16_z_tied1, svfloat16_t, __fp16,
+		 z0 = svdivr_n_f16_z (p0, z0, x0),
+		 z0 = svdivr_z (p0, z0, x0))
+
+/*
+** divr_w0_f16_z_untied:
+**	mov	(z[0-9]+\.h), w0
+**	movprfx	z0\.h, p0/z, \1
+**	fdiv	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f16_z_untied, svfloat16_t, __fp16,
+		 z0 = svdivr_n_f16_z (p0, z1, x0),
+		 z0 = svdivr_z (p0, z1, x0))
+
+/*
+** divr_h0_f16_z_tied1:
+**	mov	(z[0-9]+\.h), h0
+**	movprfx	z1\.h, p0/z, z1\.h
+**	fdivr	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_h0_f16_z_tied1, svfloat16_t, __fp16,
+		 z1 = svdivr_n_f16_z (p0, z1, d0),
+		 z1 = svdivr_z (p0, z1, d0))
+
+/*
+** divr_h0_f16_z_untied:
+**	mov	(z[0-9]+\.h), h0
+**	movprfx	z1\.h, p0/z, \1
+**	fdiv	z1\.h, p0/m, z1\.h, z2\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_h0_f16_z_untied, svfloat16_t, __fp16,
+		 z1 = svdivr_n_f16_z (p0, z2, d0),
+		 z1 = svdivr_z (p0, z2, d0))
+
+/*
+** divr_1_f16_z_tied1:
+**	fmov	(z[0-9]+\.h), #1.0(e\+0)?
+**	movprfx	z0\.h, p0/z, z0\.h
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f16_z_tied1, svfloat16_t,
+		z0 = svdivr_n_f16_z (p0, z0, 1),
+		z0 = svdivr_z (p0, z0, 1))
+
+/*
+** divr_0p5_f16_z_tied1:
+**	fmov	(z[0-9]+\.h), #5.0(e\-1)?
+**	movprfx	z0\.h, p0/z, z0\.h
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f16_z_tied1, svfloat16_t,
+		z0 = svdivr_n_f16_z (p0, z0, 0.5),
+		z0 = svdivr_z (p0, z0, 0.5))
+
+/*
+** divr_0p5_f16_z_untied:
+**	fmov	(z[0-9]+\.h), #5.0(e\-1)?
+**	movprfx	z0\.h, p0/z, \1
+**	fdiv	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f16_z_untied, svfloat16_t,
+		z0 = svdivr_n_f16_z (p0, z1, 0.5),
+		z0 = svdivr_z (p0, z1, 0.5))
+
+/*
+** divr_f16_x_tied1:
+**	fdivr	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f16_x_tied1, svfloat16_t,
+		z0 = svdivr_f16_x (p0, z0, z1),
+		z0 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_f16_x_tied2:
+**	fdiv	z1\.h, p0/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f16_x_tied2, svfloat16_t,
+		z1 = svdivr_f16_x (p0, z0, z1),
+		z1 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_f16_x_untied:
+**	movprfx	z2, z1
+**	fdiv	z2\.h, p0/m, z2\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f16_x_untied, svfloat16_t,
+		z2 = svdivr_f16_x (p0, z0, z1),
+		z2 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_w0_f16_x_tied1:
+**	mov	(z[0-9]+\.h), w0
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f16_x_tied1, svfloat16_t, __fp16,
+		 z0 = svdivr_n_f16_x (p0, z0, x0),
+		 z0 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_w0_f16_x_untied:
+**	mov	z1\.h, w0
+**	fdiv	z1\.h, p0/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f16_x_untied, svfloat16_t, __fp16,
+		 z1 = svdivr_n_f16_x (p0, z0, x0),
+		 z1 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_h0_f16_x_tied1:
+**	mov	(z[0-9]+\.h), h0
+**	fdivr	z1\.h, p0/m, z1\.h, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_h0_f16_x_tied1, svfloat16_t, __fp16,
+		 z1 = svdivr_n_f16_x (p0, z1, d0),
+		 z1 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_h0_f16_x_untied:
+**	mov	z2\.h, h0
+**	fdiv	z2\.h, p0/m, z2\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_h0_f16_x_untied, svfloat16_t, __fp16,
+		 z2 = svdivr_n_f16_x (p0, z1, d0),
+		 z2 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_1_f16_x_tied1:
+**	fmov	(z[0-9]+\.h), #1\.0(e\+0)?
+**	fdivr	z0\.h, p0/m, z0\.h, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f16_x_tied1, svfloat16_t,
+		z0 = svdivr_n_f16_x (p0, z0, 1),
+		z0 = svdivr_x (p0, z0, 1))
+
+/*
+** divr_1_f16_x_untied:
+**	fmov	z0\.h, #1\.0(e\+0)?
+**	fdiv	z0\.h, p0/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f16_x_untied, svfloat16_t,
+		z0 = svdivr_n_f16_x (p0, z1, 1),
+		z0 = svdivr_x (p0, z1, 1))
+
+/*
+** ptrue_divr_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fdivr	z0\.h, \1/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f16_x_tied1, svfloat16_t,
+		z0 = svdivr_f16_x (svptrue_b16 (), z0, z1),
+		z0 = svdivr_x (svptrue_b16 (), z0, z1))
+
+/*
+** ptrue_divr_f16_x_tied2:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fdiv	z1\.h, \1/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f16_x_tied2, svfloat16_t,
+		z1 = svdivr_f16_x (svptrue_b16 (), z0, z1),
+		z1 = svdivr_x (svptrue_b16 (), z0, z1))
+
+/*
+** ptrue_divr_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	movprfx	z2, z1
+**	fdiv	z2\.h, \1/m, z2\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f16_x_untied, svfloat16_t,
+		z2 = svdivr_f16_x (svptrue_b16 (), z0, z1),
+		z2 = svdivr_x (svptrue_b16 (), z0, z1))
+
+/*
+** ptrue_divr_w0_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	mov	(z[0-9]+\.h), w0
+**	fdivr	z0\.h, \1/m, z0\.h, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_w0_f16_x_tied1, svfloat16_t, __fp16,
+		 z0 = svdivr_n_f16_x (svptrue_b16 (), z0, x0),
+		 z0 = svdivr_x (svptrue_b16 (), z0, x0))
+
+/*
+** ptrue_divr_w0_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	mov	z1\.h, w0
+**	fdiv	z1\.h, \1/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_w0_f16_x_untied, svfloat16_t, __fp16,
+		 z1 = svdivr_n_f16_x (svptrue_b16 (), z0, x0),
+		 z1 = svdivr_x (svptrue_b16 (), z0, x0))
+
+/*
+** ptrue_divr_h0_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	mov	(z[0-9]+\.h), h0
+**	fdivr	z1\.h, \1/m, z1\.h, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_h0_f16_x_tied1, svfloat16_t, __fp16,
+		 z1 = svdivr_n_f16_x (svptrue_b16 (), z1, d0),
+		 z1 = svdivr_x (svptrue_b16 (), z1, d0))
+
+/*
+** ptrue_divr_h0_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	mov	z2\.h, h0
+**	fdiv	z2\.h, \1/m, z2\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_h0_f16_x_untied, svfloat16_t, __fp16,
+		 z2 = svdivr_n_f16_x (svptrue_b16 (), z1, d0),
+		 z2 = svdivr_x (svptrue_b16 (), z1, d0))
+
+/*
+** ptrue_divr_1_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fmov	z0\.h, #1.0(e\+0)?
+**	fdiv	z0\.h, \1/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_1_f16_x_untied, svfloat16_t,
+		z0 = svdivr_n_f16_x (svptrue_b16 (), z1, 1),
+		z0 = svdivr_x (svptrue_b16 (), z1, 1))
+
+/*
+** ptrue_b8_divr_f16_x_tied1:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fdivr	z0\.h, \1/m, z0\.h, z1\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f16_x_tied1, svfloat16_t,
+		z0 = svdivr_f16_x (svptrue_b8 (), z0, z1),
+		z0 = svdivr_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_divr_f16_x_tied2:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	fdiv	z1\.h, \1/m, z1\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f16_x_tied2, svfloat16_t,
+		z1 = svdivr_f16_x (svptrue_b8 (), z0, z1),
+		z1 = svdivr_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_divr_f16_x_untied:
+**	ptrue	(p[0-7])\.h[^\n]*
+**	movprfx	z2, z1
+**	fdiv	z2\.h, \1/m, z2\.h, z0\.h
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f16_x_untied, svfloat16_t,
+		z2 = svdivr_f16_x (svptrue_b8 (), z0, z1),
+		z2 = svdivr_x (svptrue_b8 (), z0, z1))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f32.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f32.c
new file mode 100644
index 0000000..0d84fbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f32.c
@@ -0,0 +1,425 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** divr_f32_m_tied1:
+**	fdivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f32_m_tied1, svfloat32_t,
+		z0 = svdivr_f32_m (p0, z0, z1),
+		z0 = svdivr_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (divr_f32_m_tied2, svfloat32_t,
+		z1 = svdivr_f32_m (p0, z0, z1),
+		z1 = svdivr_m (p0, z0, z1))
+
+/*
+** divr_f32_m_untied:
+**	movprfx	z0, z1
+**	fdivr	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f32_m_untied, svfloat32_t,
+		z0 = svdivr_f32_m (p0, z1, z2),
+		z0 = svdivr_m (p0, z1, z2))
+
+/*
+** divr_w0_f32_m_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f32_m_tied1, svfloat32_t, float,
+		 z0 = svdivr_n_f32_m (p0, z0, x0),
+		 z0 = svdivr_m (p0, z0, x0))
+
+/*
+** divr_w0_f32_m_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0, z1
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f32_m_untied, svfloat32_t, float,
+		 z0 = svdivr_n_f32_m (p0, z1, x0),
+		 z0 = svdivr_m (p0, z1, x0))
+
+/*
+** divr_s0_f32_m_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	fdivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_f32_m_tied1, svfloat32_t, float,
+		 z1 = svdivr_n_f32_m (p0, z1, d0),
+		 z1 = svdivr_m (p0, z1, d0))
+
+/*
+** divr_s0_f32_m_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1, z2
+**	fdivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_f32_m_untied, svfloat32_t, float,
+		 z1 = svdivr_n_f32_m (p0, z2, d0),
+		 z1 = svdivr_m (p0, z2, d0))
+
+/*
+** divr_1_f32_m_tied1:
+**	fmov	(z[0-9]+\.s), #1.0(e\+0)?
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f32_m_tied1, svfloat32_t,
+		z0 = svdivr_n_f32_m (p0, z0, 1),
+		z0 = svdivr_m (p0, z0, 1))
+
+/*
+** divr_1_f32_m_untied:
+**	fmov	(z[0-9]+\.s), #1.0(e\+0)?
+**	movprfx	z0, z1
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f32_m_untied, svfloat32_t,
+		z0 = svdivr_n_f32_m (p0, z1, 1),
+		z0 = svdivr_m (p0, z1, 1))
+
+/*
+** divr_0p5_f32_m_tied1:
+**	fmov	(z[0-9]+\.s), #5.0(e\-1)?
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f32_m_tied1, svfloat32_t,
+		z0 = svdivr_n_f32_m (p0, z0, 0.5),
+		z0 = svdivr_m (p0, z0, 0.5))
+
+/*
+** divr_0p5_f32_m_untied:
+**	fmov	(z[0-9]+\.s), #5.0(e\-1)?
+**	movprfx	z0, z1
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f32_m_untied, svfloat32_t,
+		z0 = svdivr_n_f32_m (p0, z1, 0.5),
+		z0 = svdivr_m (p0, z1, 0.5))
+
+
+/*
+** divr_f32_z_tied1:
+**	movprfx	z0\.s, p0/z, z0\.s
+**	fdivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f32_z_tied1, svfloat32_t,
+		z0 = svdivr_f32_z (p0, z0, z1),
+		z0 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_f32_z_tied2:
+**	movprfx	z1\.s, p0/z, z1\.s
+**	fdiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f32_z_tied2, svfloat32_t,
+		z1 = svdivr_f32_z (p0, z0, z1),
+		z1 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_f32_z_untied:
+**	movprfx	z0\.s, p0/z, z2\.s
+**	fdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f32_z_untied, svfloat32_t,
+		z0 = svdivr_f32_z (p0, z1, z2),
+		z0 = svdivr_z (p0, z1, z2))
+
+/*
+** divr_w0_f32_z_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z0\.s
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f32_z_tied1, svfloat32_t, float,
+		 z0 = svdivr_n_f32_z (p0, z0, x0),
+		 z0 = svdivr_z (p0, z0, x0))
+
+/*
+** divr_w0_f32_z_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, \1
+**	fdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f32_z_untied, svfloat32_t, float,
+		 z0 = svdivr_n_f32_z (p0, z1, x0),
+		 z0 = svdivr_z (p0, z1, x0))
+
+/*
+** divr_s0_f32_z_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z1\.s
+**	fdivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_f32_z_tied1, svfloat32_t, float,
+		 z1 = svdivr_n_f32_z (p0, z1, d0),
+		 z1 = svdivr_z (p0, z1, d0))
+
+/*
+** divr_s0_f32_z_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, \1
+**	fdiv	z1\.s, p0/m, z1\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_f32_z_untied, svfloat32_t, float,
+		 z1 = svdivr_n_f32_z (p0, z2, d0),
+		 z1 = svdivr_z (p0, z2, d0))
+
+/*
+** divr_1_f32_z_tied1:
+**	fmov	(z[0-9]+\.s), #1.0(e\+0)?
+**	movprfx	z0\.s, p0/z, z0\.s
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f32_z_tied1, svfloat32_t,
+		z0 = svdivr_n_f32_z (p0, z0, 1),
+		z0 = svdivr_z (p0, z0, 1))
+
+/*
+** divr_0p5_f32_z_tied1:
+**	fmov	(z[0-9]+\.s), #5.0(e\-1)?
+**	movprfx	z0\.s, p0/z, z0\.s
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f32_z_tied1, svfloat32_t,
+		z0 = svdivr_n_f32_z (p0, z0, 0.5),
+		z0 = svdivr_z (p0, z0, 0.5))
+
+/*
+** divr_0p5_f32_z_untied:
+**	fmov	(z[0-9]+\.s), #5.0(e\-1)?
+**	movprfx	z0\.s, p0/z, \1
+**	fdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f32_z_untied, svfloat32_t,
+		z0 = svdivr_n_f32_z (p0, z1, 0.5),
+		z0 = svdivr_z (p0, z1, 0.5))
+
+/*
+** divr_f32_x_tied1:
+**	fdivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f32_x_tied1, svfloat32_t,
+		z0 = svdivr_f32_x (p0, z0, z1),
+		z0 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_f32_x_tied2:
+**	fdiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f32_x_tied2, svfloat32_t,
+		z1 = svdivr_f32_x (p0, z0, z1),
+		z1 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_f32_x_untied:
+**	movprfx	z2, z1
+**	fdiv	z2\.s, p0/m, z2\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f32_x_untied, svfloat32_t,
+		z2 = svdivr_f32_x (p0, z0, z1),
+		z2 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_w0_f32_x_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f32_x_tied1, svfloat32_t, float,
+		 z0 = svdivr_n_f32_x (p0, z0, x0),
+		 z0 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_w0_f32_x_untied:
+**	mov	z1\.s, w0
+**	fdiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_f32_x_untied, svfloat32_t, float,
+		 z1 = svdivr_n_f32_x (p0, z0, x0),
+		 z1 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_s0_f32_x_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	fdivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_f32_x_tied1, svfloat32_t, float,
+		 z1 = svdivr_n_f32_x (p0, z1, d0),
+		 z1 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_s0_f32_x_untied:
+**	mov	z2\.s, s0
+**	fdiv	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_f32_x_untied, svfloat32_t, float,
+		 z2 = svdivr_n_f32_x (p0, z1, d0),
+		 z2 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_1_f32_x_tied1:
+**	fmov	(z[0-9]+\.s), #1\.0(e\+0)?
+**	fdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f32_x_tied1, svfloat32_t,
+		z0 = svdivr_n_f32_x (p0, z0, 1),
+		z0 = svdivr_x (p0, z0, 1))
+
+/*
+** divr_1_f32_x_untied:
+**	fmov	z0\.s, #1\.0(e\+0)?
+**	fdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f32_x_untied, svfloat32_t,
+		z0 = svdivr_n_f32_x (p0, z1, 1),
+		z0 = svdivr_x (p0, z1, 1))
+
+/*
+** ptrue_divr_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fdivr	z0\.s, \1/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f32_x_tied1, svfloat32_t,
+		z0 = svdivr_f32_x (svptrue_b32 (), z0, z1),
+		z0 = svdivr_x (svptrue_b32 (), z0, z1))
+
+/*
+** ptrue_divr_f32_x_tied2:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fdiv	z1\.s, \1/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f32_x_tied2, svfloat32_t,
+		z1 = svdivr_f32_x (svptrue_b32 (), z0, z1),
+		z1 = svdivr_x (svptrue_b32 (), z0, z1))
+
+/*
+** ptrue_divr_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	movprfx	z2, z1
+**	fdiv	z2\.s, \1/m, z2\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f32_x_untied, svfloat32_t,
+		z2 = svdivr_f32_x (svptrue_b32 (), z0, z1),
+		z2 = svdivr_x (svptrue_b32 (), z0, z1))
+
+/*
+** ptrue_divr_w0_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	mov	(z[0-9]+\.s), w0
+**	fdivr	z0\.s, \1/m, z0\.s, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_w0_f32_x_tied1, svfloat32_t, float,
+		 z0 = svdivr_n_f32_x (svptrue_b32 (), z0, x0),
+		 z0 = svdivr_x (svptrue_b32 (), z0, x0))
+
+/*
+** ptrue_divr_w0_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	mov	z1\.s, w0
+**	fdiv	z1\.s, \1/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_w0_f32_x_untied, svfloat32_t, float,
+		 z1 = svdivr_n_f32_x (svptrue_b32 (), z0, x0),
+		 z1 = svdivr_x (svptrue_b32 (), z0, x0))
+
+/*
+** ptrue_divr_s0_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	mov	(z[0-9]+\.s), s0
+**	fdivr	z1\.s, \1/m, z1\.s, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_s0_f32_x_tied1, svfloat32_t, float,
+		 z1 = svdivr_n_f32_x (svptrue_b32 (), z1, d0),
+		 z1 = svdivr_x (svptrue_b32 (), z1, d0))
+
+/*
+** ptrue_divr_s0_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	mov	z2\.s, s0
+**	fdiv	z2\.s, \1/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_s0_f32_x_untied, svfloat32_t, float,
+		 z2 = svdivr_n_f32_x (svptrue_b32 (), z1, d0),
+		 z2 = svdivr_x (svptrue_b32 (), z1, d0))
+
+/*
+** ptrue_divr_1_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fmov	z0\.s, #1.0(e\+0)?
+**	fdiv	z0\.s, \1/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_1_f32_x_untied, svfloat32_t,
+		z0 = svdivr_n_f32_x (svptrue_b32 (), z1, 1),
+		z0 = svdivr_x (svptrue_b32 (), z1, 1))
+
+/*
+** ptrue_b8_divr_f32_x_tied1:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fdivr	z0\.s, \1/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f32_x_tied1, svfloat32_t,
+		z0 = svdivr_f32_x (svptrue_b8 (), z0, z1),
+		z0 = svdivr_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_divr_f32_x_tied2:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	fdiv	z1\.s, \1/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f32_x_tied2, svfloat32_t,
+		z1 = svdivr_f32_x (svptrue_b8 (), z0, z1),
+		z1 = svdivr_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_divr_f32_x_untied:
+**	ptrue	(p[0-7])\.s[^\n]*
+**	movprfx	z2, z1
+**	fdiv	z2\.s, \1/m, z2\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f32_x_untied, svfloat32_t,
+		z2 = svdivr_f32_x (svptrue_b8 (), z0, z1),
+		z2 = svdivr_x (svptrue_b8 (), z0, z1))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f64.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f64.c
new file mode 100644
index 0000000..23f2eac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_f64.c
@@ -0,0 +1,425 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** divr_f64_m_tied1:
+**	fdivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f64_m_tied1, svfloat64_t,
+		z0 = svdivr_f64_m (p0, z0, z1),
+		z0 = svdivr_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (divr_f64_m_tied2, svfloat64_t,
+		z1 = svdivr_f64_m (p0, z0, z1),
+		z1 = svdivr_m (p0, z0, z1))
+
+/*
+** divr_f64_m_untied:
+**	movprfx	z0, z1
+**	fdivr	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f64_m_untied, svfloat64_t,
+		z0 = svdivr_f64_m (p0, z1, z2),
+		z0 = svdivr_m (p0, z1, z2))
+
+/*
+** divr_x0_f64_m_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_f64_m_tied1, svfloat64_t, double,
+		 z0 = svdivr_n_f64_m (p0, z0, x0),
+		 z0 = svdivr_m (p0, z0, x0))
+
+/*
+** divr_x0_f64_m_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0, z1
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_f64_m_untied, svfloat64_t, double,
+		 z0 = svdivr_n_f64_m (p0, z1, x0),
+		 z0 = svdivr_m (p0, z1, x0))
+
+/*
+** divr_d0_f64_m_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	fdivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_f64_m_tied1, svfloat64_t, double,
+		 z1 = svdivr_n_f64_m (p0, z1, d0),
+		 z1 = svdivr_m (p0, z1, d0))
+
+/*
+** divr_d0_f64_m_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1, z2
+**	fdivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_f64_m_untied, svfloat64_t, double,
+		 z1 = svdivr_n_f64_m (p0, z2, d0),
+		 z1 = svdivr_m (p0, z2, d0))
+
+/*
+** divr_1_f64_m_tied1:
+**	fmov	(z[0-9]+\.d), #1.0(e\+0)?
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f64_m_tied1, svfloat64_t,
+		z0 = svdivr_n_f64_m (p0, z0, 1),
+		z0 = svdivr_m (p0, z0, 1))
+
+/*
+** divr_1_f64_m_untied:
+**	fmov	(z[0-9]+\.d), #1.0(e\+0)?
+**	movprfx	z0, z1
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f64_m_untied, svfloat64_t,
+		z0 = svdivr_n_f64_m (p0, z1, 1),
+		z0 = svdivr_m (p0, z1, 1))
+
+/*
+** divr_0p5_f64_m_tied1:
+**	fmov	(z[0-9]+\.d), #5.0(e\-1)?
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f64_m_tied1, svfloat64_t,
+		z0 = svdivr_n_f64_m (p0, z0, 0.5),
+		z0 = svdivr_m (p0, z0, 0.5))
+
+/*
+** divr_0p5_f64_m_untied:
+**	fmov	(z[0-9]+\.d), #5.0(e\-1)?
+**	movprfx	z0, z1
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f64_m_untied, svfloat64_t,
+		z0 = svdivr_n_f64_m (p0, z1, 0.5),
+		z0 = svdivr_m (p0, z1, 0.5))
+
+
+/*
+** divr_f64_z_tied1:
+**	movprfx	z0\.d, p0/z, z0\.d
+**	fdivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f64_z_tied1, svfloat64_t,
+		z0 = svdivr_f64_z (p0, z0, z1),
+		z0 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_f64_z_tied2:
+**	movprfx	z1\.d, p0/z, z1\.d
+**	fdiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f64_z_tied2, svfloat64_t,
+		z1 = svdivr_f64_z (p0, z0, z1),
+		z1 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_f64_z_untied:
+**	movprfx	z0\.d, p0/z, z2\.d
+**	fdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f64_z_untied, svfloat64_t,
+		z0 = svdivr_f64_z (p0, z1, z2),
+		z0 = svdivr_z (p0, z1, z2))
+
+/*
+** divr_x0_f64_z_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z0\.d
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_f64_z_tied1, svfloat64_t, double,
+		 z0 = svdivr_n_f64_z (p0, z0, x0),
+		 z0 = svdivr_z (p0, z0, x0))
+
+/*
+** divr_x0_f64_z_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, \1
+**	fdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_f64_z_untied, svfloat64_t, double,
+		 z0 = svdivr_n_f64_z (p0, z1, x0),
+		 z0 = svdivr_z (p0, z1, x0))
+
+/*
+** divr_d0_f64_z_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z1\.d
+**	fdivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_f64_z_tied1, svfloat64_t, double,
+		 z1 = svdivr_n_f64_z (p0, z1, d0),
+		 z1 = svdivr_z (p0, z1, d0))
+
+/*
+** divr_d0_f64_z_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, \1
+**	fdiv	z1\.d, p0/m, z1\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_f64_z_untied, svfloat64_t, double,
+		 z1 = svdivr_n_f64_z (p0, z2, d0),
+		 z1 = svdivr_z (p0, z2, d0))
+
+/*
+** divr_1_f64_z_tied1:
+**	fmov	(z[0-9]+\.d), #1.0(e\+0)?
+**	movprfx	z0\.d, p0/z, z0\.d
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f64_z_tied1, svfloat64_t,
+		z0 = svdivr_n_f64_z (p0, z0, 1),
+		z0 = svdivr_z (p0, z0, 1))
+
+/*
+** divr_0p5_f64_z_tied1:
+**	fmov	(z[0-9]+\.d), #5.0(e\-1)?
+**	movprfx	z0\.d, p0/z, z0\.d
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f64_z_tied1, svfloat64_t,
+		z0 = svdivr_n_f64_z (p0, z0, 0.5),
+		z0 = svdivr_z (p0, z0, 0.5))
+
+/*
+** divr_0p5_f64_z_untied:
+**	fmov	(z[0-9]+\.d), #5.0(e\-1)?
+**	movprfx	z0\.d, p0/z, \1
+**	fdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_0p5_f64_z_untied, svfloat64_t,
+		z0 = svdivr_n_f64_z (p0, z1, 0.5),
+		z0 = svdivr_z (p0, z1, 0.5))
+
+/*
+** divr_f64_x_tied1:
+**	fdivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f64_x_tied1, svfloat64_t,
+		z0 = svdivr_f64_x (p0, z0, z1),
+		z0 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_f64_x_tied2:
+**	fdiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f64_x_tied2, svfloat64_t,
+		z1 = svdivr_f64_x (p0, z0, z1),
+		z1 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_f64_x_untied:
+**	movprfx	z2, z1
+**	fdiv	z2\.d, p0/m, z2\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_f64_x_untied, svfloat64_t,
+		z2 = svdivr_f64_x (p0, z0, z1),
+		z2 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_x0_f64_x_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_f64_x_tied1, svfloat64_t, double,
+		 z0 = svdivr_n_f64_x (p0, z0, x0),
+		 z0 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_x0_f64_x_untied:
+**	mov	z1\.d, x0
+**	fdiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_f64_x_untied, svfloat64_t, double,
+		 z1 = svdivr_n_f64_x (p0, z0, x0),
+		 z1 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_d0_f64_x_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	fdivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_f64_x_tied1, svfloat64_t, double,
+		 z1 = svdivr_n_f64_x (p0, z1, d0),
+		 z1 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_d0_f64_x_untied:
+**	mov	z2\.d, d0
+**	fdiv	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_f64_x_untied, svfloat64_t, double,
+		 z2 = svdivr_n_f64_x (p0, z1, d0),
+		 z2 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_1_f64_x_tied1:
+**	fmov	(z[0-9]+\.d), #1\.0(e\+0)?
+**	fdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f64_x_tied1, svfloat64_t,
+		z0 = svdivr_n_f64_x (p0, z0, 1),
+		z0 = svdivr_x (p0, z0, 1))
+
+/*
+** divr_1_f64_x_untied:
+**	fmov	z0\.d, #1\.0(e\+0)?
+**	fdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_1_f64_x_untied, svfloat64_t,
+		z0 = svdivr_n_f64_x (p0, z1, 1),
+		z0 = svdivr_x (p0, z1, 1))
+
+/*
+** ptrue_divr_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fdivr	z0\.d, \1/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f64_x_tied1, svfloat64_t,
+		z0 = svdivr_f64_x (svptrue_b64 (), z0, z1),
+		z0 = svdivr_x (svptrue_b64 (), z0, z1))
+
+/*
+** ptrue_divr_f64_x_tied2:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fdiv	z1\.d, \1/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f64_x_tied2, svfloat64_t,
+		z1 = svdivr_f64_x (svptrue_b64 (), z0, z1),
+		z1 = svdivr_x (svptrue_b64 (), z0, z1))
+
+/*
+** ptrue_divr_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	movprfx	z2, z1
+**	fdiv	z2\.d, \1/m, z2\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_f64_x_untied, svfloat64_t,
+		z2 = svdivr_f64_x (svptrue_b64 (), z0, z1),
+		z2 = svdivr_x (svptrue_b64 (), z0, z1))
+
+/*
+** ptrue_divr_x0_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	mov	(z[0-9]+\.d), x0
+**	fdivr	z0\.d, \1/m, z0\.d, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_x0_f64_x_tied1, svfloat64_t, double,
+		 z0 = svdivr_n_f64_x (svptrue_b64 (), z0, x0),
+		 z0 = svdivr_x (svptrue_b64 (), z0, x0))
+
+/*
+** ptrue_divr_x0_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	mov	z1\.d, x0
+**	fdiv	z1\.d, \1/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_x0_f64_x_untied, svfloat64_t, double,
+		 z1 = svdivr_n_f64_x (svptrue_b64 (), z0, x0),
+		 z1 = svdivr_x (svptrue_b64 (), z0, x0))
+
+/*
+** ptrue_divr_d0_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	mov	(z[0-9]+\.d), d0
+**	fdivr	z1\.d, \1/m, z1\.d, \2
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_d0_f64_x_tied1, svfloat64_t, double,
+		 z1 = svdivr_n_f64_x (svptrue_b64 (), z1, d0),
+		 z1 = svdivr_x (svptrue_b64 (), z1, d0))
+
+/*
+** ptrue_divr_d0_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	mov	z2\.d, d0
+**	fdiv	z2\.d, \1/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (ptrue_divr_d0_f64_x_untied, svfloat64_t, double,
+		 z2 = svdivr_n_f64_x (svptrue_b64 (), z1, d0),
+		 z2 = svdivr_x (svptrue_b64 (), z1, d0))
+
+/*
+** ptrue_divr_1_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fmov	z0\.d, #1.0(e\+0)?
+**	fdiv	z0\.d, \1/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_divr_1_f64_x_untied, svfloat64_t,
+		z0 = svdivr_n_f64_x (svptrue_b64 (), z1, 1),
+		z0 = svdivr_x (svptrue_b64 (), z1, 1))
+
+/*
+** ptrue_b8_divr_f64_x_tied1:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fdivr	z0\.d, \1/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f64_x_tied1, svfloat64_t,
+		z0 = svdivr_f64_x (svptrue_b8 (), z0, z1),
+		z0 = svdivr_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_divr_f64_x_tied2:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	fdiv	z1\.d, \1/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f64_x_tied2, svfloat64_t,
+		z1 = svdivr_f64_x (svptrue_b8 (), z0, z1),
+		z1 = svdivr_x (svptrue_b8 (), z0, z1))
+
+/*
+** ptrue_b8_divr_f64_x_untied:
+**	ptrue	(p[0-7])\.d[^\n]*
+**	movprfx	z2, z1
+**	fdiv	z2\.d, \1/m, z2\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (ptrue_b8_divr_f64_x_untied, svfloat64_t,
+		z2 = svdivr_f64_x (svptrue_b8 (), z0, z1),
+		z2 = svdivr_x (svptrue_b8 (), z0, z1))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_s32.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_s32.c
new file mode 100644
index 0000000..834e457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_s32.c
@@ -0,0 +1,264 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** divr_s32_m_tied1:
+**	sdivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s32_m_tied1, svint32_t,
+		z0 = svdivr_s32_m (p0, z0, z1),
+		z0 = svdivr_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (divr_s32_m_tied2, svint32_t,
+		z1 = svdivr_s32_m (p0, z0, z1),
+		z1 = svdivr_m (p0, z0, z1))
+
+/*
+** divr_s32_m_untied:
+**	movprfx	z0, z1
+**	sdivr	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s32_m_untied, svint32_t,
+		z0 = svdivr_s32_m (p0, z1, z2),
+		z0 = svdivr_m (p0, z1, z2))
+
+/*
+** divr_w0_s32_m_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	sdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_s32_m_tied1, svint32_t, int32_t,
+		 z0 = svdivr_n_s32_m (p0, z0, x0),
+		 z0 = svdivr_m (p0, z0, x0))
+
+/*
+** divr_w0_s32_m_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0, z1
+**	sdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_s32_m_untied, svint32_t, int32_t,
+		 z0 = svdivr_n_s32_m (p0, z1, x0),
+		 z0 = svdivr_m (p0, z1, x0))
+
+/*
+** divr_s0_s32_m_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	sdivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_s32_m_tied1, svint32_t, int32_t,
+		 z1 = svdivr_n_s32_m (p0, z1, d0),
+		 z1 = svdivr_m (p0, z1, d0))
+
+/*
+** divr_s0_s32_m_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1, z2
+**	sdivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_s32_m_untied, svint32_t, int32_t,
+		 z1 = svdivr_n_s32_m (p0, z2, d0),
+		 z1 = svdivr_m (p0, z2, d0))
+
+/*
+** divr_2_s32_m_tied1:
+**	mov	(z[0-9]+\.s), #2
+**	sdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_s32_m_tied1, svint32_t,
+		z0 = svdivr_n_s32_m (p0, z0, 2),
+		z0 = svdivr_m (p0, z0, 2))
+
+/*
+** divr_2_s32_m_untied:
+**	mov	(z[0-9]+\.s), #2
+**	movprfx	z0, z1
+**	sdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_s32_m_untied, svint32_t,
+		z0 = svdivr_n_s32_m (p0, z1, 2),
+		z0 = svdivr_m (p0, z1, 2))
+
+/*
+** divr_m1_s32_m:
+**	mov	(z[0-9]+)\.b, #(-1|255)
+**	sdivr	z0\.s, p0/m, z0\.s, \1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_m1_s32_m, svint32_t,
+		z0 = svdivr_n_s32_m (p0, z0, -1),
+		z0 = svdivr_m (p0, z0, -1))
+
+/*
+** divr_s32_z_tied1:
+**	movprfx	z0\.s, p0/z, z0\.s
+**	sdivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s32_z_tied1, svint32_t,
+		z0 = svdivr_s32_z (p0, z0, z1),
+		z0 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_s32_z_tied2:
+**	movprfx	z1\.s, p0/z, z1\.s
+**	sdiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s32_z_tied2, svint32_t,
+		z1 = svdivr_s32_z (p0, z0, z1),
+		z1 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_s32_z_untied:
+**	movprfx	z0\.s, p0/z, z2\.s
+**	sdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s32_z_untied, svint32_t,
+		z0 = svdivr_s32_z (p0, z1, z2),
+		z0 = svdivr_z (p0, z1, z2))
+
+/*
+** divr_w0_s32_z_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z0\.s
+**	sdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_s32_z_tied1, svint32_t, int32_t,
+		 z0 = svdivr_n_s32_z (p0, z0, x0),
+		 z0 = svdivr_z (p0, z0, x0))
+
+/*
+** divr_w0_s32_z_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, \1
+**	sdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_s32_z_untied, svint32_t, int32_t,
+		 z0 = svdivr_n_s32_z (p0, z1, x0),
+		 z0 = svdivr_z (p0, z1, x0))
+
+/*
+** divr_s0_s32_z_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z1\.s
+**	sdivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_s32_z_tied1, svint32_t, int32_t,
+		 z1 = svdivr_n_s32_z (p0, z1, d0),
+		 z1 = svdivr_z (p0, z1, d0))
+
+/*
+** divr_s0_s32_z_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, \1
+**	sdiv	z1\.s, p0/m, z1\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_s32_z_untied, svint32_t, int32_t,
+		 z1 = svdivr_n_s32_z (p0, z2, d0),
+		 z1 = svdivr_z (p0, z2, d0))
+
+/*
+** divr_s32_x_tied1:
+**	sdivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s32_x_tied1, svint32_t,
+		z0 = svdivr_s32_x (p0, z0, z1),
+		z0 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_s32_x_tied2:
+**	sdiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s32_x_tied2, svint32_t,
+		z1 = svdivr_s32_x (p0, z0, z1),
+		z1 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_s32_x_untied:
+**	movprfx	z2, z1
+**	sdiv	z2\.s, p0/m, z2\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s32_x_untied, svint32_t,
+		z2 = svdivr_s32_x (p0, z0, z1),
+		z2 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_w0_s32_x_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	sdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_s32_x_tied1, svint32_t, int32_t,
+		 z0 = svdivr_n_s32_x (p0, z0, x0),
+		 z0 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_w0_s32_x_untied:
+**	mov	z1\.s, w0
+**	sdiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_s32_x_untied, svint32_t, int32_t,
+		 z1 = svdivr_n_s32_x (p0, z0, x0),
+		 z1 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_s0_s32_x_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	sdivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_s32_x_tied1, svint32_t, int32_t,
+		 z1 = svdivr_n_s32_x (p0, z1, d0),
+		 z1 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_s0_s32_x_untied:
+**	mov	z2\.s, s0
+**	sdiv	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_s32_x_untied, svint32_t, int32_t,
+		 z2 = svdivr_n_s32_x (p0, z1, d0),
+		 z2 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_2_s32_x_tied1:
+**	mov	(z[0-9]+\.s), #2
+**	sdivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_s32_x_tied1, svint32_t,
+		z0 = svdivr_n_s32_x (p0, z0, 2),
+		z0 = svdivr_x (p0, z0, 2))
+
+/*
+** divr_2_s32_x_untied:
+**	mov	z0\.s, #2
+**	sdiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_s32_x_untied, svint32_t,
+		z0 = svdivr_n_s32_x (p0, z1, 2),
+		z0 = svdivr_x (p0, z1, 2))
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_s64.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_s64.c
new file mode 100644
index 0000000..654a119
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_s64.c
@@ -0,0 +1,264 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** divr_s64_m_tied1:
+**	sdivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s64_m_tied1, svint64_t,
+		z0 = svdivr_s64_m (p0, z0, z1),
+		z0 = svdivr_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (divr_s64_m_tied2, svint64_t,
+		z1 = svdivr_s64_m (p0, z0, z1),
+		z1 = svdivr_m (p0, z0, z1))
+
+/*
+** divr_s64_m_untied:
+**	movprfx	z0, z1
+**	sdivr	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s64_m_untied, svint64_t,
+		z0 = svdivr_s64_m (p0, z1, z2),
+		z0 = svdivr_m (p0, z1, z2))
+
+/*
+** divr_x0_s64_m_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	sdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_s64_m_tied1, svint64_t, int64_t,
+		 z0 = svdivr_n_s64_m (p0, z0, x0),
+		 z0 = svdivr_m (p0, z0, x0))
+
+/*
+** divr_x0_s64_m_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0, z1
+**	sdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_s64_m_untied, svint64_t, int64_t,
+		 z0 = svdivr_n_s64_m (p0, z1, x0),
+		 z0 = svdivr_m (p0, z1, x0))
+
+/*
+** divr_d0_s64_m_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	sdivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_s64_m_tied1, svint64_t, int64_t,
+		 z1 = svdivr_n_s64_m (p0, z1, d0),
+		 z1 = svdivr_m (p0, z1, d0))
+
+/*
+** divr_d0_s64_m_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1, z2
+**	sdivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_s64_m_untied, svint64_t, int64_t,
+		 z1 = svdivr_n_s64_m (p0, z2, d0),
+		 z1 = svdivr_m (p0, z2, d0))
+
+/*
+** divr_2_s64_m_tied1:
+**	mov	(z[0-9]+\.d), #2
+**	sdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_s64_m_tied1, svint64_t,
+		z0 = svdivr_n_s64_m (p0, z0, 2),
+		z0 = svdivr_m (p0, z0, 2))
+
+/*
+** divr_2_s64_m_untied:
+**	mov	(z[0-9]+\.d), #2
+**	movprfx	z0, z1
+**	sdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_s64_m_untied, svint64_t,
+		z0 = svdivr_n_s64_m (p0, z1, 2),
+		z0 = svdivr_m (p0, z1, 2))
+
+/*
+** divr_m1_s64_m:
+**	mov	(z[0-9]+)\.b, #(-1|255)
+**	sdivr	z0\.d, p0/m, z0\.d, \1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_m1_s64_m, svint64_t,
+		z0 = svdivr_n_s64_m (p0, z0, -1),
+		z0 = svdivr_m (p0, z0, -1))
+
+/*
+** divr_s64_z_tied1:
+**	movprfx	z0\.d, p0/z, z0\.d
+**	sdivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s64_z_tied1, svint64_t,
+		z0 = svdivr_s64_z (p0, z0, z1),
+		z0 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_s64_z_tied2:
+**	movprfx	z1\.d, p0/z, z1\.d
+**	sdiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s64_z_tied2, svint64_t,
+		z1 = svdivr_s64_z (p0, z0, z1),
+		z1 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_s64_z_untied:
+**	movprfx	z0\.d, p0/z, z2\.d
+**	sdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s64_z_untied, svint64_t,
+		z0 = svdivr_s64_z (p0, z1, z2),
+		z0 = svdivr_z (p0, z1, z2))
+
+/*
+** divr_x0_s64_z_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z0\.d
+**	sdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_s64_z_tied1, svint64_t, int64_t,
+		 z0 = svdivr_n_s64_z (p0, z0, x0),
+		 z0 = svdivr_z (p0, z0, x0))
+
+/*
+** divr_x0_s64_z_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, \1
+**	sdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_s64_z_untied, svint64_t, int64_t,
+		 z0 = svdivr_n_s64_z (p0, z1, x0),
+		 z0 = svdivr_z (p0, z1, x0))
+
+/*
+** divr_d0_s64_z_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z1\.d
+**	sdivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_s64_z_tied1, svint64_t, int64_t,
+		 z1 = svdivr_n_s64_z (p0, z1, d0),
+		 z1 = svdivr_z (p0, z1, d0))
+
+/*
+** divr_d0_s64_z_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, \1
+**	sdiv	z1\.d, p0/m, z1\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_s64_z_untied, svint64_t, int64_t,
+		 z1 = svdivr_n_s64_z (p0, z2, d0),
+		 z1 = svdivr_z (p0, z2, d0))
+
+/*
+** divr_s64_x_tied1:
+**	sdivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s64_x_tied1, svint64_t,
+		z0 = svdivr_s64_x (p0, z0, z1),
+		z0 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_s64_x_tied2:
+**	sdiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s64_x_tied2, svint64_t,
+		z1 = svdivr_s64_x (p0, z0, z1),
+		z1 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_s64_x_untied:
+**	movprfx	z2, z1
+**	sdiv	z2\.d, p0/m, z2\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_s64_x_untied, svint64_t,
+		z2 = svdivr_s64_x (p0, z0, z1),
+		z2 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_x0_s64_x_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	sdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_s64_x_tied1, svint64_t, int64_t,
+		 z0 = svdivr_n_s64_x (p0, z0, x0),
+		 z0 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_x0_s64_x_untied:
+**	mov	z1\.d, x0
+**	sdiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_s64_x_untied, svint64_t, int64_t,
+		 z1 = svdivr_n_s64_x (p0, z0, x0),
+		 z1 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_d0_s64_x_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	sdivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_s64_x_tied1, svint64_t, int64_t,
+		 z1 = svdivr_n_s64_x (p0, z1, d0),
+		 z1 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_d0_s64_x_untied:
+**	mov	z2\.d, d0
+**	sdiv	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_s64_x_untied, svint64_t, int64_t,
+		 z2 = svdivr_n_s64_x (p0, z1, d0),
+		 z2 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_2_s64_x_tied1:
+**	mov	(z[0-9]+\.d), #2
+**	sdivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_s64_x_tied1, svint64_t,
+		z0 = svdivr_n_s64_x (p0, z0, 2),
+		z0 = svdivr_x (p0, z0, 2))
+
+/*
+** divr_2_s64_x_untied:
+**	mov	z0\.d, #2
+**	sdiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_s64_x_untied, svint64_t,
+		z0 = svdivr_n_s64_x (p0, z1, 2),
+		z0 = svdivr_x (p0, z1, 2))
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_u32.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_u32.c
new file mode 100644
index 0000000..efae0fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_u32.c
@@ -0,0 +1,264 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** divr_u32_m_tied1:
+**	udivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u32_m_tied1, svuint32_t,
+		z0 = svdivr_u32_m (p0, z0, z1),
+		z0 = svdivr_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (divr_u32_m_tied2, svuint32_t,
+		z1 = svdivr_u32_m (p0, z0, z1),
+		z1 = svdivr_m (p0, z0, z1))
+
+/*
+** divr_u32_m_untied:
+**	movprfx	z0, z1
+**	udivr	z0\.s, p0/m, z0\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u32_m_untied, svuint32_t,
+		z0 = svdivr_u32_m (p0, z1, z2),
+		z0 = svdivr_m (p0, z1, z2))
+
+/*
+** divr_w0_u32_m_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	udivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_u32_m_tied1, svuint32_t, uint32_t,
+		 z0 = svdivr_n_u32_m (p0, z0, x0),
+		 z0 = svdivr_m (p0, z0, x0))
+
+/*
+** divr_w0_u32_m_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0, z1
+**	udivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_u32_m_untied, svuint32_t, uint32_t,
+		 z0 = svdivr_n_u32_m (p0, z1, x0),
+		 z0 = svdivr_m (p0, z1, x0))
+
+/*
+** divr_s0_u32_m_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	udivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_u32_m_tied1, svuint32_t, uint32_t,
+		 z1 = svdivr_n_u32_m (p0, z1, d0),
+		 z1 = svdivr_m (p0, z1, d0))
+
+/*
+** divr_s0_u32_m_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1, z2
+**	udivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_u32_m_untied, svuint32_t, uint32_t,
+		 z1 = svdivr_n_u32_m (p0, z2, d0),
+		 z1 = svdivr_m (p0, z2, d0))
+
+/*
+** divr_2_u32_m_tied1:
+**	mov	(z[0-9]+\.s), #2
+**	udivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_u32_m_tied1, svuint32_t,
+		z0 = svdivr_n_u32_m (p0, z0, 2),
+		z0 = svdivr_m (p0, z0, 2))
+
+/*
+** divr_2_u32_m_untied:
+**	mov	(z[0-9]+\.s), #2
+**	movprfx	z0, z1
+**	udivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_u32_m_untied, svuint32_t,
+		z0 = svdivr_n_u32_m (p0, z1, 2),
+		z0 = svdivr_m (p0, z1, 2))
+
+/*
+** divr_m1_u32_m:
+**	mov	(z[0-9]+)\.b, #(-1|255)
+**	udivr	z0\.s, p0/m, z0\.s, \1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_m1_u32_m, svuint32_t,
+		z0 = svdivr_n_u32_m (p0, z0, -1),
+		z0 = svdivr_m (p0, z0, -1))
+
+/*
+** divr_u32_z_tied1:
+**	movprfx	z0\.s, p0/z, z0\.s
+**	udivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u32_z_tied1, svuint32_t,
+		z0 = svdivr_u32_z (p0, z0, z1),
+		z0 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_u32_z_tied2:
+**	movprfx	z1\.s, p0/z, z1\.s
+**	udiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u32_z_tied2, svuint32_t,
+		z1 = svdivr_u32_z (p0, z0, z1),
+		z1 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_u32_z_untied:
+**	movprfx	z0\.s, p0/z, z2\.s
+**	udiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u32_z_untied, svuint32_t,
+		z0 = svdivr_u32_z (p0, z1, z2),
+		z0 = svdivr_z (p0, z1, z2))
+
+/*
+** divr_w0_u32_z_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, z0\.s
+**	udivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_u32_z_tied1, svuint32_t, uint32_t,
+		 z0 = svdivr_n_u32_z (p0, z0, x0),
+		 z0 = svdivr_z (p0, z0, x0))
+
+/*
+** divr_w0_u32_z_untied:
+**	mov	(z[0-9]+\.s), w0
+**	movprfx	z0\.s, p0/z, \1
+**	udiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_u32_z_untied, svuint32_t, uint32_t,
+		 z0 = svdivr_n_u32_z (p0, z1, x0),
+		 z0 = svdivr_z (p0, z1, x0))
+
+/*
+** divr_s0_u32_z_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, z1\.s
+**	udivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_u32_z_tied1, svuint32_t, uint32_t,
+		 z1 = svdivr_n_u32_z (p0, z1, d0),
+		 z1 = svdivr_z (p0, z1, d0))
+
+/*
+** divr_s0_u32_z_untied:
+**	mov	(z[0-9]+\.s), s0
+**	movprfx	z1\.s, p0/z, \1
+**	udiv	z1\.s, p0/m, z1\.s, z2\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_u32_z_untied, svuint32_t, uint32_t,
+		 z1 = svdivr_n_u32_z (p0, z2, d0),
+		 z1 = svdivr_z (p0, z2, d0))
+
+/*
+** divr_u32_x_tied1:
+**	udivr	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u32_x_tied1, svuint32_t,
+		z0 = svdivr_u32_x (p0, z0, z1),
+		z0 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_u32_x_tied2:
+**	udiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u32_x_tied2, svuint32_t,
+		z1 = svdivr_u32_x (p0, z0, z1),
+		z1 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_u32_x_untied:
+**	movprfx	z2, z1
+**	udiv	z2\.s, p0/m, z2\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u32_x_untied, svuint32_t,
+		z2 = svdivr_u32_x (p0, z0, z1),
+		z2 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_w0_u32_x_tied1:
+**	mov	(z[0-9]+\.s), w0
+**	udivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_u32_x_tied1, svuint32_t, uint32_t,
+		 z0 = svdivr_n_u32_x (p0, z0, x0),
+		 z0 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_w0_u32_x_untied:
+**	mov	z1\.s, w0
+**	udiv	z1\.s, p0/m, z1\.s, z0\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_w0_u32_x_untied, svuint32_t, uint32_t,
+		 z1 = svdivr_n_u32_x (p0, z0, x0),
+		 z1 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_s0_u32_x_tied1:
+**	mov	(z[0-9]+\.s), s0
+**	udivr	z1\.s, p0/m, z1\.s, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_u32_x_tied1, svuint32_t, uint32_t,
+		 z1 = svdivr_n_u32_x (p0, z1, d0),
+		 z1 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_s0_u32_x_untied:
+**	mov	z2\.s, s0
+**	udiv	z2\.s, p0/m, z2\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_s0_u32_x_untied, svuint32_t, uint32_t,
+		 z2 = svdivr_n_u32_x (p0, z1, d0),
+		 z2 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_2_u32_x_tied1:
+**	mov	(z[0-9]+\.s), #2
+**	udivr	z0\.s, p0/m, z0\.s, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_u32_x_tied1, svuint32_t,
+		z0 = svdivr_n_u32_x (p0, z0, 2),
+		z0 = svdivr_x (p0, z0, 2))
+
+/*
+** divr_2_u32_x_untied:
+**	mov	z0\.s, #2
+**	udiv	z0\.s, p0/m, z0\.s, z1\.s
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_u32_x_untied, svuint32_t,
+		z0 = svdivr_n_u32_x (p0, z1, 2),
+		z0 = svdivr_x (p0, z1, 2))
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_u64.c b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_u64.c
new file mode 100644
index 0000000..09ba465
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve-acle/asm/divr_u64.c
@@ -0,0 +1,264 @@
+/* { dg-do compile } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sve_acle.h"
+
+/*
+** divr_u64_m_tied1:
+**	udivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u64_m_tied1, svuint64_t,
+		z0 = svdivr_u64_m (p0, z0, z1),
+		z0 = svdivr_m (p0, z0, z1))
+
+/* Bad RA choice: no preferred output sequence.  */
+TEST_UNIFORM_Z (divr_u64_m_tied2, svuint64_t,
+		z1 = svdivr_u64_m (p0, z0, z1),
+		z1 = svdivr_m (p0, z0, z1))
+
+/*
+** divr_u64_m_untied:
+**	movprfx	z0, z1
+**	udivr	z0\.d, p0/m, z0\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u64_m_untied, svuint64_t,
+		z0 = svdivr_u64_m (p0, z1, z2),
+		z0 = svdivr_m (p0, z1, z2))
+
+/*
+** divr_x0_u64_m_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	udivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_u64_m_tied1, svuint64_t, uint64_t,
+		 z0 = svdivr_n_u64_m (p0, z0, x0),
+		 z0 = svdivr_m (p0, z0, x0))
+
+/*
+** divr_x0_u64_m_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0, z1
+**	udivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_u64_m_untied, svuint64_t, uint64_t,
+		 z0 = svdivr_n_u64_m (p0, z1, x0),
+		 z0 = svdivr_m (p0, z1, x0))
+
+/*
+** divr_d0_u64_m_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	udivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_u64_m_tied1, svuint64_t, uint64_t,
+		 z1 = svdivr_n_u64_m (p0, z1, d0),
+		 z1 = svdivr_m (p0, z1, d0))
+
+/*
+** divr_d0_u64_m_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1, z2
+**	udivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_u64_m_untied, svuint64_t, uint64_t,
+		 z1 = svdivr_n_u64_m (p0, z2, d0),
+		 z1 = svdivr_m (p0, z2, d0))
+
+/*
+** divr_2_u64_m_tied1:
+**	mov	(z[0-9]+\.d), #2
+**	udivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_u64_m_tied1, svuint64_t,
+		z0 = svdivr_n_u64_m (p0, z0, 2),
+		z0 = svdivr_m (p0, z0, 2))
+
+/*
+** divr_2_u64_m_untied:
+**	mov	(z[0-9]+\.d), #2
+**	movprfx	z0, z1
+**	udivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_u64_m_untied, svuint64_t,
+		z0 = svdivr_n_u64_m (p0, z1, 2),
+		z0 = svdivr_m (p0, z1, 2))
+
+/*
+** divr_m1_u64_m:
+**	mov	(z[0-9]+)\.b, #(-1|255)
+**	udivr	z0\.d, p0/m, z0\.d, \1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_m1_u64_m, svuint64_t,
+		z0 = svdivr_n_u64_m (p0, z0, -1),
+		z0 = svdivr_m (p0, z0, -1))
+
+/*
+** divr_u64_z_tied1:
+**	movprfx	z0\.d, p0/z, z0\.d
+**	udivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u64_z_tied1, svuint64_t,
+		z0 = svdivr_u64_z (p0, z0, z1),
+		z0 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_u64_z_tied2:
+**	movprfx	z1\.d, p0/z, z1\.d
+**	udiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u64_z_tied2, svuint64_t,
+		z1 = svdivr_u64_z (p0, z0, z1),
+		z1 = svdivr_z (p0, z0, z1))
+
+/*
+** divr_u64_z_untied:
+**	movprfx	z0\.d, p0/z, z2\.d
+**	udiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u64_z_untied, svuint64_t,
+		z0 = svdivr_u64_z (p0, z1, z2),
+		z0 = svdivr_z (p0, z1, z2))
+
+/*
+** divr_x0_u64_z_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, z0\.d
+**	udivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_u64_z_tied1, svuint64_t, uint64_t,
+		 z0 = svdivr_n_u64_z (p0, z0, x0),
+		 z0 = svdivr_z (p0, z0, x0))
+
+/*
+** divr_x0_u64_z_untied:
+**	mov	(z[0-9]+\.d), x0
+**	movprfx	z0\.d, p0/z, \1
+**	udiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_u64_z_untied, svuint64_t, uint64_t,
+		 z0 = svdivr_n_u64_z (p0, z1, x0),
+		 z0 = svdivr_z (p0, z1, x0))
+
+/*
+** divr_d0_u64_z_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, z1\.d
+**	udivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_u64_z_tied1, svuint64_t, uint64_t,
+		 z1 = svdivr_n_u64_z (p0, z1, d0),
+		 z1 = svdivr_z (p0, z1, d0))
+
+/*
+** divr_d0_u64_z_untied:
+**	mov	(z[0-9]+\.d), d0
+**	movprfx	z1\.d, p0/z, \1
+**	udiv	z1\.d, p0/m, z1\.d, z2\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_u64_z_untied, svuint64_t, uint64_t,
+		 z1 = svdivr_n_u64_z (p0, z2, d0),
+		 z1 = svdivr_z (p0, z2, d0))
+
+/*
+** divr_u64_x_tied1:
+**	udivr	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u64_x_tied1, svuint64_t,
+		z0 = svdivr_u64_x (p0, z0, z1),
+		z0 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_u64_x_tied2:
+**	udiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u64_x_tied2, svuint64_t,
+		z1 = svdivr_u64_x (p0, z0, z1),
+		z1 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_u64_x_untied:
+**	movprfx	z2, z1
+**	udiv	z2\.d, p0/m, z2\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_u64_x_untied, svuint64_t,
+		z2 = svdivr_u64_x (p0, z0, z1),
+		z2 = svdivr_x (p0, z0, z1))
+
+/*
+** divr_x0_u64_x_tied1:
+**	mov	(z[0-9]+\.d), x0
+**	udivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_u64_x_tied1, svuint64_t, uint64_t,
+		 z0 = svdivr_n_u64_x (p0, z0, x0),
+		 z0 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_x0_u64_x_untied:
+**	mov	z1\.d, x0
+**	udiv	z1\.d, p0/m, z1\.d, z0\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_x0_u64_x_untied, svuint64_t, uint64_t,
+		 z1 = svdivr_n_u64_x (p0, z0, x0),
+		 z1 = svdivr_x (p0, z0, x0))
+
+/*
+** divr_d0_u64_x_tied1:
+**	mov	(z[0-9]+\.d), d0
+**	udivr	z1\.d, p0/m, z1\.d, \1
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_u64_x_tied1, svuint64_t, uint64_t,
+		 z1 = svdivr_n_u64_x (p0, z1, d0),
+		 z1 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_d0_u64_x_untied:
+**	mov	z2\.d, d0
+**	udiv	z2\.d, p0/m, z2\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_ZS (divr_d0_u64_x_untied, svuint64_t, uint64_t,
+		 z2 = svdivr_n_u64_x (p0, z1, d0),
+		 z2 = svdivr_x (p0, z1, d0))
+
+/*
+** divr_2_u64_x_tied1:
+**	mov	(z[0-9]+\.d), #2
+**	udivr	z0\.d, p0/m, z0\.d, \1
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_u64_x_tied1, svuint64_t,
+		z0 = svdivr_n_u64_x (p0, z0, 2),
+		z0 = svdivr_x (p0, z0, 2))
+
+/*
+** divr_2_u64_x_untied:
+**	mov	z0\.d, #2
+**	udiv	z0\.d, p0/m, z0\.d, z1\.d
+**	ret
+*/
+TEST_UNIFORM_Z (divr_2_u64_x_untied, svuint64_t,
+		z0 = svdivr_n_u64_x (p0, z1, 2),
+		z0 = svdivr_x (p0, z1, 2))
+
-- 
2.7.4

