From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ot1-x32f.google.com (mail-ot1-x32f.google.com [IPv6:2607:f8b0:4864:20::32f]) by sourceware.org (Postfix) with ESMTPS id 540E53858417 for ; Wed, 13 Dec 2023 09:03:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 540E53858417 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 540E53858417 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::32f ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702458201; cv=none; b=R8JjC9nfPtmqT10KK2g/+z7sDw7ko02UB2Sqtobcs4WcAzUVU8x+67gDFVi1laPk2f+b8z0nbFCdiY43SKl+qExcCC0PXtUcK5vmfNzpnJvznC10c5PcY1xyHv6it+xMIkXIw0nUZubZOVrA3aUIJAQ8yqrIINdhEmmmhzQPPig= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702458201; c=relaxed/simple; bh=lPWdiTboB02t3JnouLDhXc5XR1X9bSdO0A4kR+6MSmQ=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=xh+oTmi7vcPjJhLTQBTnMwr6/ycuS+mMhRiCXIqo+620EeNI3cXm+34hJZGyQ4Uzxf1CUochSGRfUhtcMH8p3EhS3WzJ1TDs9Lal5Mu4jI2nTcdJ8I76izKqOHeeR84wfiFemuofKydS2zKq3VFDZar6OzbGB+gryyK2O0XBdFI= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-6da330ff8fdso505341a34.0 for ; Wed, 13 Dec 2023 01:03:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1702458192; x=1703062992; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=z03Yoo9YwgS/jppEelu9+u6z5DiPrcLkMw7NQw8Iqsg=; b=mXHEEdFj2/5fazH74SKI41x+jN+28TvVcPMmoqa2e/TEimT+oEmBvPXzkqyKU9fqB3 QuMvFGERwVi3pPGjKICRJrgglFLvcsqxk6RnWrxa4L2darJbMYcpui0b/7guuq6lJKI5 LzPMSDR/DiSxOTthuPGz4V9uX0jzhAeCFD09SxSPgiu6J3YMAEUGYqVbgnSGNyzrTvHs r9fpIEOP4/oPxoa++9FVvpbM1cWWPvkQR7RGk9EBMQIg1X45o3R8j4H+rc+5d/yLag8/ Eel10t1EdvQVFVKfztCTdjvpJ6ojy2+rul7bcuEPB1JpHg4bXXreNDobeMTa1C0E4vcx 3a+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702458192; x=1703062992; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z03Yoo9YwgS/jppEelu9+u6z5DiPrcLkMw7NQw8Iqsg=; b=UGsl0/9A++95vfxGJsLNN5JY7iE7oIIn1PslUn05A3jg/Be0eqMyApk/uarrDsrOav sqTd9TTeMYHefRemfq8MVe4ljjoK8iO1mAMz2gQCSdO2suL8XNya/9kzSOjzzfQy7mBG Mm5cvzjnWrgoJ40hfiP+/6IRrozpLVQM9WEYnvz9ERadOAo+MfZ7sADzhFS6+tg+mtEf /rxqhs78fRqboso/xuxZ6wwsS/wXf9pF1+morA+PJ5iprG5KvwuiKsS8HOqpCzCTfU3e 1C1T5i94VC293fM1xXx6FixA/QC8veLrvYg8lyxGUN8v8VY2jfEKtpxfOPIu9Svqsxxo peog== X-Gm-Message-State: AOJu0YyuyKLTZy8QuQtZEZ5yVDsRMB1GlMosR9FFQtJeiGeUnCaOXeEe 6iaedR/WNYJlPV3r2Z1cbK80FtQn2/PiKlyl2Y5P4g== X-Google-Smtp-Source: AGHT+IFm+XgBLRZN4Q9jVqMBYKB87bvXguOkFI4I65Qnx2R6/8U6cguwLci3J+lcqzXxCZWkmRVs9rbGFYSzLjwD5DU= X-Received: by 2002:a05:6359:c25:b0:170:17ea:f4d4 with SMTP id gn37-20020a0563590c2500b0017017eaf4d4mr6628798rwb.33.1702458192439; Wed, 13 Dec 2023 01:03:12 -0800 (PST) MIME-Version: 1.0 References: <20231213082244.3760797-1-shihua@iscas.ac.cn> In-Reply-To: <20231213082244.3760797-1-shihua@iscas.ac.cn> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Wed, 13 Dec 2023 10:03:01 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: fix scalar crypto pattern To: Liao Shihua Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, shiyulong@iscas.ac.cn, jiawei@iscas.ac.cn, chenyixuan@iscas.an.cn, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, Dec 13, 2023 at 9:22=E2=80=AFAM Liao Shihua wr= ote: > > In Scalar Crypto Built-In functions, some require immediate parameters, > But register_operand are incorrectly used in the pattern. > > E.g.: > __builtin_riscv_aes64ks1i(rs1,1) > Before: > li a5,1 > aes64ks1i a0,a0,a5 > > Assembler messages: > Error: instruction aes64ks1i requires absolute expression > > After: > aes64ks1i a0,a0,1 Looks good to me (also tested with rv32 and rv64). (I was actually surprised that the D03 constraint was not sufficient) Reviewed-by: Christoph Muellner Tested-by: Christoph Muellner Nit: I would prefer to separate arguments with a comma followed by a space. Even if the existing code was not written like that. E.g. __builtin_riscv_sm4ed(rs1,rs2,1); -> __builtin_riscv_sm4ed(rs1, rs2, 1= ); I propose to remove the builtin tests for scalar crypto and scalar bitmanip as part of the patchset that adds the intrinsic tests (no value in duplicated tests). > gcc/ChangeLog: > > * config/riscv/crypto.md: Use immediate_operand instead of regist= er_operand. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zknd32.c: Use immediate instead of parameter. > * gcc.target/riscv/zknd64.c: Ditto. > * gcc.target/riscv/zkne32.c: Ditto. > * gcc.target/riscv/zkne64.c: Ditto. > * gcc.target/riscv/zksed32.c: Ditto. > * gcc.target/riscv/zksed64.c: Ditto. > > --- > gcc/config/riscv/crypto.md | 16 ++++++++-------- > gcc/testsuite/gcc.target/riscv/zknd32.c | 8 ++++---- > gcc/testsuite/gcc.target/riscv/zknd64.c | 4 ++-- > gcc/testsuite/gcc.target/riscv/zkne32.c | 8 ++++---- > gcc/testsuite/gcc.target/riscv/zkne64.c | 4 ++-- > gcc/testsuite/gcc.target/riscv/zksed32.c | 8 ++++---- > gcc/testsuite/gcc.target/riscv/zksed64.c | 8 ++++---- > 7 files changed, 28 insertions(+), 28 deletions(-) > > diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md > index 03a1d03397d..c45f12e421f 100644 > --- a/gcc/config/riscv/crypto.md > +++ b/gcc/config/riscv/crypto.md > @@ -148,7 +148,7 @@ > [(set (match_operand:SI 0 "register_operand" "=3Dr") > (unspec:SI [(match_operand:SI 1 "register_operand" "r") > (match_operand:SI 2 "register_operand" "r") > - (match_operand:SI 3 "register_operand" "D03")] > + (match_operand:SI 3 "immediate_operand" "D03")] > UNSPEC_AES_DSI))] > "TARGET_ZKND && !TARGET_64BIT" > "aes32dsi\t%0,%1,%2,%3" > @@ -158,7 +158,7 @@ > [(set (match_operand:SI 0 "register_operand" "=3Dr") > (unspec:SI [(match_operand:SI 1 "register_operand" "r") > (match_operand:SI 2 "register_operand" "r") > - (match_operand:SI 3 "register_operand" "D03")] > + (match_operand:SI 3 "immediate_operand" "D03")] > UNSPEC_AES_DSMI))] > "TARGET_ZKND && !TARGET_64BIT" > "aes32dsmi\t%0,%1,%2,%3" > @@ -193,7 +193,7 @@ > (define_insn "riscv_aes64ks1i" > [(set (match_operand:DI 0 "register_operand" "=3Dr") > (unspec:DI [(match_operand:DI 1 "register_operand" "r") > - (match_operand:SI 2 "register_operand" "DsA")] > + (match_operand:SI 2 "immediate_operand" "DsA")] > UNSPEC_AES_KS1I))] > "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" > "aes64ks1i\t%0,%1,%2" > @@ -214,7 +214,7 @@ > [(set (match_operand:SI 0 "register_operand" "=3Dr") > (unspec:SI [(match_operand:SI 1 "register_operand" "r") > (match_operand:SI 2 "register_operand" "r") > - (match_operand:SI 3 "register_operand" "D03")] > + (match_operand:SI 3 "immediate_operand" "D03")] > UNSPEC_AES_ESI))] > "TARGET_ZKNE && !TARGET_64BIT" > "aes32esi\t%0,%1,%2,%3" > @@ -224,7 +224,7 @@ > [(set (match_operand:SI 0 "register_operand" "=3Dr") > (unspec:SI [(match_operand:SI 1 "register_operand" "r") > (match_operand:SI 2 "register_operand" "r") > - (match_operand:SI 3 "register_operand" "D03")] > + (match_operand:SI 3 "immediate_operand" "D03")] > UNSPEC_AES_ESMI))] > "TARGET_ZKNE && !TARGET_64BIT" > "aes32esmi\t%0,%1,%2,%3" > @@ -431,7 +431,7 @@ > [(set (match_operand:SI 0 "register_operand" "=3Dr") > (unspec:SI [(match_operand:SI 1 "register_operand" "r") > (match_operand:SI 2 "register_operand" "r") > - (match_operand:SI 3 "register_operand" "D03")] > + (match_operand:SI 3 "immediate_operand" "D03")] > SM4_OP))] > "TARGET_ZKSED && !TARGET_64BIT" > "\t%0,%1,%2,%3" > @@ -442,7 +442,7 @@ > (sign_extend:DI > (unspec:SI [(match_operand:SI 1 "register_operand" "r") > (match_operand:SI 2 "register_operand" "r") > - (match_operand:SI 3 "register_operand" "D03")] > + (match_operand:SI 3 "immediate_operand" "D03")] > SM4_OP)))] > "TARGET_ZKSED && TARGET_64BIT" > "\t%0,%1,%2,%3" > @@ -452,7 +452,7 @@ > [(set (match_operand:SI 0 "register_operand" "=3Dr") > (unspec:SI [(match_operand:SI 1 "register_operand" "r") > (match_operand:SI 2 "register_operand" "r") > - (match_operand:SI 3 "register_operand" "D03")] > + (match_operand:SI 3 "immediate_operand" "D03")] > SM4_OP))] > "TARGET_ZKSED" > { > diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c b/gcc/testsuite/gcc.= target/riscv/zknd32.c > index e60c027e091..9711b120001 100644 > --- a/gcc/testsuite/gcc.target/riscv/zknd32.c > +++ b/gcc/testsuite/gcc.target/riscv/zknd32.c > @@ -4,14 +4,14 @@ > > #include > > -uint32_t foo1(uint32_t rs1, uint32_t rs2, int bs) > +uint32_t foo1(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_aes32dsi(rs1,rs2,bs); > + return __builtin_riscv_aes32dsi(rs1,rs2,1); > } > > -uint32_t foo2(uint32_t rs1, uint32_t rs2, int bs) > +uint32_t foo2(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_aes32dsmi(rs1,rs2,bs); > + return __builtin_riscv_aes32dsmi(rs1,rs2,1); > } > > /* { dg-final { scan-assembler-times "aes32dsi" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.= target/riscv/zknd64.c > index 707418cd51e..d56c03f201e 100644 > --- a/gcc/testsuite/gcc.target/riscv/zknd64.c > +++ b/gcc/testsuite/gcc.target/riscv/zknd64.c > @@ -14,9 +14,9 @@ uint64_t foo2(uint64_t rs1, uint64_t rs2) > return __builtin_riscv_aes64dsm(rs1,rs2); > } > > -uint64_t foo3(uint64_t rs1, unsigned rnum) > +uint64_t foo3(uint64_t rs1) > { > - return __builtin_riscv_aes64ks1i(rs1,rnum); > + return __builtin_riscv_aes64ks1i(rs1,1); > } > > uint64_t foo4(uint64_t rs1, uint64_t rs2) > diff --git a/gcc/testsuite/gcc.target/riscv/zkne32.c b/gcc/testsuite/gcc.= target/riscv/zkne32.c > index 252e9ffa43b..378c3a2fdd3 100644 > --- a/gcc/testsuite/gcc.target/riscv/zkne32.c > +++ b/gcc/testsuite/gcc.target/riscv/zkne32.c > @@ -4,14 +4,14 @@ > > #include > > -uint32_t foo1(uint32_t rs1, uint32_t rs2, unsigned bs) > +uint32_t foo1(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_aes32esi(rs1, rs2, bs); > + return __builtin_riscv_aes32esi(rs1, rs2,1); > } > > -uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) > +uint32_t foo2(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_aes32esmi(rs1, rs2, bs); > + return __builtin_riscv_aes32esmi(rs1, rs2, 1); > } > > /* { dg-final { scan-assembler-times "aes32esi" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zkne64.c b/gcc/testsuite/gcc.= target/riscv/zkne64.c > index b25f6b5c29a..d5435b399c6 100644 > --- a/gcc/testsuite/gcc.target/riscv/zkne64.c > +++ b/gcc/testsuite/gcc.target/riscv/zkne64.c > @@ -14,9 +14,9 @@ uint64_t foo2(uint64_t rs1, uint64_t rs2) > return __builtin_riscv_aes64esm(rs1,rs2); > } > > -uint64_t foo3(uint64_t rs1, unsigned rnum) > +uint64_t foo3(uint64_t rs1) > { > - return __builtin_riscv_aes64ks1i(rs1,rnum); > + return __builtin_riscv_aes64ks1i(rs1,1); > } > > uint64_t foo4(uint64_t rs1, uint64_t rs2) > diff --git a/gcc/testsuite/gcc.target/riscv/zksed32.c b/gcc/testsuite/gcc= .target/riscv/zksed32.c > index 0e8f01cd548..a3583d9f4ae 100644 > --- a/gcc/testsuite/gcc.target/riscv/zksed32.c > +++ b/gcc/testsuite/gcc.target/riscv/zksed32.c > @@ -4,14 +4,14 @@ > > #include > > -uint32_t foo1(uint32_t rs1, uint32_t rs2, unsigned bs) > +uint32_t foo1(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sm4ks(rs1,rs2,bs); > + return __builtin_riscv_sm4ks(rs1,rs2,1); > } > > -uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) > +uint32_t foo2(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sm4ed(rs1,rs2,bs); > + return __builtin_riscv_sm4ed(rs1,rs2,1); > } > > > diff --git a/gcc/testsuite/gcc.target/riscv/zksed64.c b/gcc/testsuite/gcc= .target/riscv/zksed64.c > index 9e4d1961419..9b06e47ce70 100644 > --- a/gcc/testsuite/gcc.target/riscv/zksed64.c > +++ b/gcc/testsuite/gcc.target/riscv/zksed64.c > @@ -4,14 +4,14 @@ > > #include > > -uint32_t foo1(uint32_t rs1, uint32_t rs2, unsigned bs) > +uint32_t foo1(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sm4ks(rs1,rs2,bs); > + return __builtin_riscv_sm4ks(rs1,rs2,1); > } > > -uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) > +uint32_t foo2(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sm4ed(rs1,rs2,bs); > + return __builtin_riscv_sm4ed(rs1,rs2,1); > } > > > -- > 2.34.1 >