From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by sourceware.org (Postfix) with ESMTPS id 33DE13861863 for ; Thu, 15 Feb 2024 10:42:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33DE13861863 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 33DE13861863 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::52b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707993771; cv=none; b=ImZ46L8yj85C2xXjJW5iHYP7Y6VHvQ++ehs4ww+y5bvdH+QaDypKPdI7sJg7k1Lu7yzGH8yhLLFqRjdv8AHrTAm1Ary+mQvmofcIKM3tukvK1O8OjdB3bO98HV1gfxjNcrztzekFXP+FkN4ga1XIel/ptXcyvH/AWf2JSEuen9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1707993771; c=relaxed/simple; bh=AXdPifM/9UM7y4QnWthNiyzUu5e3uht5XupvQhkS+W0=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=o1UI7z0UlZBq9BGZD78eQveN54vAMK4Sh3yfRohnQGJnVOIngmCVzaGiHKDcd7isCxaUMiX3JlCl6ub9vt/p5O5LJ/9hmtYj56zBUfOfwTto5NFnyGFgZpXNbA9A+s8P2QSe8wVilOCbJdCWYd+zEbB2WwW3SnHkZfn5U4o0SVg= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-5c6bd3100fcso497800a12.3 for ; Thu, 15 Feb 2024 02:42:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1707993768; x=1708598568; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=thl1u9DIgVQH+rkN/di/RPTZ3u8GzZHN5HsY3fx3Cls=; b=VS+/itDhabR9HGbmC2J5IB7kVRvCsHUt/9Hfg6KmkDZvlSFmRnN3ZdaouuOixGiw1T liyXopgJu2nqY2JneGk9QCM8jcTfsl8PR2Aq3++2zvnv0ich2Xiuu3BtBRHZ/Y4C9c46 52yZ1Tgab+u5EpbyBAalZ/q5ElI1xyA304Vrl6A+jCGBDVRghDB/Qm9luSVUAwc3ONx0 rvIBGnEIR2rIxQxMGeI/+q/ThmZKEBIr/0e8mSk6YiblhuANcnoZUU237IDOd28iq6UX wLvg7UJcUaXsWyaioBnGsOtZG+HIJHdQAirYt7IKcHVeb+QhsZC8cJL9WMCcOiyoAeqT N4Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1707993768; x=1708598568; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=thl1u9DIgVQH+rkN/di/RPTZ3u8GzZHN5HsY3fx3Cls=; b=JK6XE93T+BdzUjl8PPL+zN+ZJ29LYZB+d1AqZh0DhMjZM1pvsvYJ0KYWbsUs1Gi0f0 nOXksD3vtOehyyqTa1bEUPGeAWZiO1+sxftSsXsNqvTSSQfnq3LhZuL8ADtV7rTrnNMD QswmXUX8+O/tw/QFdMcpWAhrttpenx+70xk5E/xWiD2pvwipODkMqBNSkkHMaoOVzp9o Zq5gkCLklQnvqRlOa2lJypZ6LUgPELEgVuIcg2LnlC/zGGrESkFGA9h5CkjkWmPCBAk5 G8v4C5WDELOszu4x+fxegllcljxJvCwwBTFfMx49fkf7SpHr02Zb3oyjsr+hnUndhc+Y opXQ== X-Gm-Message-State: AOJu0YzZI30bHeWW4hO2/n+DefkMpbLb+fNbXHbFZ1qr+HFgFR8zskFK KTsm/IJ0Azw9wHp2lX93ZY/qVH9NPQPsPTril9DFROlT5kitg170494nGDHhXyXlshc19biD9Qe SyLYC5zj622h6Itj1Na3u78bRulyOMXm+o6GWoA== X-Google-Smtp-Source: AGHT+IHb0U6Sc02HtCIx/MyAaqhRm5twPIqcIllML91smkTsZJGUy/PjHAa/XOu0l0SMaUGLUHHzOFrlptBrU3xIMmo= X-Received: by 2002:a17:90a:ac06:b0:299:4cd:69e0 with SMTP id o6-20020a17090aac0600b0029904cd69e0mr1258652pjq.0.1707993767965; Thu, 15 Feb 2024 02:42:47 -0800 (PST) MIME-Version: 1.0 References: <20240215095619.2811703-1-kito.cheng@sifive.com> In-Reply-To: <20240215095619.2811703-1-kito.cheng@sifive.com> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Thu, 15 Feb 2024 11:42:36 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Add new option -march=help to print all supported extensions To: Kito Cheng Cc: gcc-patches@gcc.gnu.org, palmer@dabbelt.com, kito.cheng@gmail.com, jeffreyalaw@gmail.com, i@maskray.me Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Feb 15, 2024 at 10:56=E2=80=AFAM Kito Cheng = wrote: > > The output of -march=3Dhelp is like below: > > ``` > All available -march extensions for RISC-V: > Name Version > i 2.0, 2.1 > e 2.0 > m 2.0 > a 2.0, 2.1 > f 2.0, 2.2 > d 2.0, 2.2 > ... > ``` > > Also support -print-supported-extensions and --print-supported-extensions= for > clang compatibility. If I remember correctly, then this feature was requested several times in the past. Thanks for working on this! Reviewed-by: Christoph M=C3=BCllner I have done a quick feature test (no bootstrapping, no check for compiler warnings) as well. Below you find all supported RISC-V extension in today's master branch: All available -march extensions for RISC-V: Name Version i 2.0, 2.1 e 2.0 m 2.0 a 2.0, 2.1 f 2.0, 2.2 d 2.0, 2.2 c 2.0 v 1.0 h 1.0 zic64b 1.0 zicbom 1.0 zicbop 1.0 zicboz 1.0 ziccamoa 1.0 ziccif 1.0 zicclsm 1.0 ziccrse 1.0 zicntr 2.0 zicond 1.0 zicsr 2.0 zifencei 2.0 zihintntl 1.0 zihintpause 2.0 zihpm 2.0 zmmul 1.0 za128rs 1.0 za64rs 1.0 zawrs 1.0 zfa 1.0 zfh 1.0 zfhmin 1.0 zfinx 1.0 zdinx 1.0 zca 1.0 zcb 1.0 zcd 1.0 zce 1.0 zcf 1.0 zcmp 1.0 zcmt 1.0 zba 1.0 zbb 1.0 zbc 1.0 zbkb 1.0 zbkc 1.0 zbkc 1.0 zbkx 1.0 zbs 1.0 zk 1.0 zkn 1.0 zknd 1.0 zkne 1.0 zknh 1.0 zkr 1.0 zks 1.0 zksed 1.0 zksh 1.0 zkt 1.0 ztso 1.0 zvbb 1.0 zvbc 1.0 zve32f 1.0 zve32x 1.0 zve64d 1.0 zve64f 1.0 zve64x 1.0 zvfbfmin 1.0 zvfh 1.0 zvfhmin 1.0 zvkb 1.0 zvkg 1.0 zvkn 1.0 zvknc 1.0 zvkned 1.0 zvkng 1.0 zvknha 1.0 zvknhb 1.0 zvks 1.0 zvksc 1.0 zvksed 1.0 zvksg 1.0 zvksh 1.0 zvkt 1.0 zvl1024b 1.0 zvl128b 1.0 zvl16384b 1.0 zvl2048b 1.0 zvl256b 1.0 zvl32768b 1.0 zvl32b 1.0 zvl4096b 1.0 zvl512b 1.0 zvl64b 1.0 zvl65536b 1.0 zvl8192b 1.0 zhinx 1.0 zhinxmin 1.0 smaia 1.0 smepmp 1.0 smstateen 1.0 ssaia 1.0 sscofpmf 1.0 ssstateen 1.0 sstc 1.0 svinval 1.0 svnapot 1.0 svpbmt 1.0 xcvalu 1.0 xcvelw 1.0 xcvmac 1.0 xcvsimd 1.0 xtheadba 1.0 xtheadbb 1.0 xtheadbs 1.0 xtheadcmo 1.0 xtheadcondmov 1.0 xtheadfmemidx 1.0 xtheadfmv 1.0 xtheadint 1.0 xtheadmac 1.0 xtheadmemidx 1.0 xtheadmempair 1.0 xtheadsync 1.0 xtheadvector 1.0 xventanacondops 1.0 > > gcc/ChangeLog: > > PR target/109349 > > * common/config/riscv/riscv-common.cc (riscv_arch_help): New. > * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New. > (RISCV_MINOR_VERSION_BASE): Ditto. > (RISCV_REVISION_VERSION_BASE): Ditto. > * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum > rather than magic number. > * config/riscv/riscv.h (riscv_arch_help): New. > (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help. > (DRIVER_SELF_SPECS): Handle -march=3Dhelp, -print-supported-exten= sions and > --print-supported-extensions. > * config/riscv/riscv.opt (march=3Dhelp): New. > (print-supported-extensions): New. > (-print-supported-extensions): New. > * doc/invoke.texi (RISC-V Options): Document -march=3Dhelp. > --- > gcc/common/config/riscv/riscv-common.cc | 46 +++++++++++++++++++++++++ > gcc/config/riscv/riscv-c.cc | 2 +- > gcc/config/riscv/riscv-protos.h | 7 ++++ > gcc/config/riscv/riscv.h | 7 +++- > gcc/config/riscv/riscv.opt | 12 +++++++ > gcc/doc/invoke.texi | 3 +- > 6 files changed, 74 insertions(+), 3 deletions(-) > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/= riscv/riscv-common.cc > index 631ce8309a0..8974fa4a128 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see > #include > > #define INCLUDE_STRING > +#define INCLUDE_SET > +#define INCLUDE_MAP > #include "config.h" > #include "system.h" > #include "coretypes.h" > @@ -2225,6 +2227,50 @@ riscv_get_valid_option_values (int option_code, > return v; > } > > +const char * > +riscv_arch_help (int argc, const char **argv) > +{ > + /* Collect all exts, and sort it in canonical order. */ > + struct extension_comparator { > + bool operator()(const std::string& a, const std::string& b) const { > + return subset_cmp(a, b) >=3D 1; > + } > + }; > + std::map, extension_comparator> all_ex= ts; > + for (const riscv_ext_version &ext : riscv_ext_version_table) > + { > + if (!ext.name) > + break; > + if (ext.name[0] =3D=3D 'g') > + continue; > + unsigned version_value =3D (ext.major_version * RISCV_MAJOR_VERSIO= N_BASE) > + + (ext.minor_version > + * RISCV_MINOR_VERSION_BASE); > + all_exts[ext.name].insert(version_value); > + } > + > + printf("All available -march extensions for RISC-V:\n"); > + printf("\t%-20sVersion\n", "Name"); > + for (auto const &ext_info : all_exts) > + { > + printf("\t%-20s\t", ext_info.first.c_str()); > + bool first =3D true; > + for (auto version : ext_info.second) > + { > + if (first) > + first =3D false; > + else > + printf(", "); > + unsigned major =3D version / RISCV_MAJOR_VERSION_BASE; > + unsigned minor =3D (version % RISCV_MAJOR_VERSION_BASE) > + / RISCV_MINOR_VERSION_BASE; > + printf("%u.%u", major, minor); > + } > + printf("\n"); > + } > + exit (0); > +} > + > /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ > static const struct default_options riscv_option_optimization_table[] = =3D > { > diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc > index 94c3871c760..3ef06dcfd2d 100644 > --- a/gcc/config/riscv/riscv-c.cc > +++ b/gcc/config/riscv/riscv-c.cc > @@ -37,7 +37,7 @@ along with GCC; see the file COPYING3. If not see > static int > riscv_ext_version_value (unsigned major, unsigned minor) > { > - return (major * 1000000) + (minor * 1000); > + return (major * RISCV_MAJOR_VERSION_BASE) + (minor * RISCV_MINOR_VERSI= ON_BASE); > } > > /* Implement TARGET_CPU_CPP_BUILTINS. */ > diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-pro= tos.h > index ae1685850ac..80efdf2b7e5 100644 > --- a/gcc/config/riscv/riscv-protos.h > +++ b/gcc/config/riscv/riscv-protos.h > @@ -780,4 +780,11 @@ const struct riscv_tune_info * > riscv_parse_tune (const char *, bool); > const cpu_vector_cost *get_vector_costs (); > > +enum > +{ > + RISCV_MAJOR_VERSION_BASE =3D 1000000, > + RISCV_MINOR_VERSION_BASE =3D 1000, > + RISCV_REVISION_VERSION_BASE =3D 1, > +}; > + > #endif /* ! GCC_RISCV_PROTOS_H */ > diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h > index 669308cc96d..da089a03e9d 100644 > --- a/gcc/config/riscv/riscv.h > +++ b/gcc/config/riscv/riscv.h > @@ -50,12 +50,14 @@ extern const char *riscv_expand_arch (int argc, const= char **argv); > extern const char *riscv_expand_arch_from_cpu (int argc, const char **ar= gv); > extern const char *riscv_default_mtune (int argc, const char **argv); > extern const char *riscv_multi_lib_check (int argc, const char **argv); > +extern const char *riscv_arch_help (int argc, const char **argv); > > # define EXTRA_SPEC_FUNCTIONS \ > { "riscv_expand_arch", riscv_expand_arch }, \ > { "riscv_expand_arch_from_cpu", riscv_expand_arch_from_cpu }, = \ > { "riscv_default_mtune", riscv_default_mtune }, \ > - { "riscv_multi_lib_check", riscv_multi_lib_check }, > + { "riscv_multi_lib_check", riscv_multi_lib_check }, \ > + { "riscv_arch_help", riscv_arch_help }, > > /* Support for a compile-time default CPU, et cetera. The rules are: > --with-arch is ignored if -march or -mcpu is specified. > @@ -109,6 +111,9 @@ ASM_MISA_SPEC > > #undef DRIVER_SELF_SPECS > #define DRIVER_SELF_SPECS \ > +"%{march=3Dhelp:%:riscv_arch_help()} " \ > +"%{print-supported-extensions:%:riscv_arch_help()} " \ > +"%{-print-supported-extensions:%:riscv_arch_help()} " \ > "%{march=3D*:%:riscv_expand_arch(%*)} " \ > "%{!march=3D*:%{mcpu=3D*:%:riscv_expand_arch_from_cpu(%*)}} " > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > index f6ff70b2b30..20685c42aed 100644 > --- a/gcc/config/riscv/riscv.opt > +++ b/gcc/config/riscv/riscv.opt > @@ -86,6 +86,18 @@ Target RejectNegative Joined Negative(march=3D) > -march=3D Generate code for given RISC-V ISA (e.g. RV64IM). ISA = strings must be > lower-case. > > +march=3Dhelp > +Target RejectNegative > +-march=3Dhelp Print supported -march extensions. > + > +; -print-supported-extensions and --print-supported-extensions are added= for > +; clang compatibility. > +print-supported-extensions > +Target Undocumented RejectNegative Alias(march=3Dhelp) > + > +-print-supported-extensions > +Target Undocumented RejectNegative Alias(march=3Dhelp) > + > mtune=3D > Target RejectNegative Joined Var(riscv_tune_string) Save > -mtune=3DPROCESSOR Optimize the output for PROCESSOR. > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index 0de184f6241..1c5423a2a66 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -30204,7 +30204,8 @@ with @option{--with-isa-spec=3D} specifying a dif= ferent default version. > @item -march=3D@var{ISA-string} > Generate code for given RISC-V ISA (e.g.@: @samp{rv64im}). ISA strings = must be > lower-case. Examples include @samp{rv64i}, @samp{rv32g}, @samp{rv32e}, = and > -@samp{rv32imaf}. > +@samp{rv32imaf}. Additionally, a special value @option{help} > +(@option{-march=3Dhelp}) is accepted to list all supported extensions. > > The syntax of the ISA string is defined as follows: > > -- > 2.34.1 >