From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf2a.google.com (mail-qv1-xf2a.google.com [IPv6:2607:f8b0:4864:20::f2a]) by sourceware.org (Postfix) with ESMTPS id 0E34838582B4 for ; Wed, 15 Jun 2022 08:30:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0E34838582B4 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-qv1-xf2a.google.com with SMTP id v12so1716449qvh.9 for ; Wed, 15 Jun 2022 01:30:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :content-transfer-encoding; bh=dYqRq9hpaJIYtJ6rL+Z37mnb9Icf1cRhpT/fmARh72s=; b=JQby7DlG+kvHVcDynwJwtWlkDTWI/Q7Hz+ZyQGfpszBzNM2oG6dY3e+B2X6BISKMPD 1XRLE+ebpBOnxjYN1qBJA6mxavvd3QiqAFYAL4OIdWicdEoO/D++YtI6Aq8pcQyIuGAR wpE8ir+kilYD8kgiLrJ0S8MItOdhexf9EaPHf7brg/+aci0hRuQ0gM8UitQ8onPwGUGt jT1bwwZoRSL0jXhO2DNP0sx3OnWa8iifonetWIUC3brJAFGtRyWVhsl99zoaOPSDOhuS bTsk0Y66NuA7xK2OGoX8vsodcCLu0TsslnynHPDyn1V9YO2iGkOlTRiup8tmJj0inFsw JvCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:content-transfer-encoding; bh=dYqRq9hpaJIYtJ6rL+Z37mnb9Icf1cRhpT/fmARh72s=; b=krVVwIVnPcdxrZmA2iahLiEbov4W98FbZFwsSHfhtK4mt3kEETcP0A9cRw+mF6x5MB El8x+9hpygY3Y1g326pQ9jOycpz4ovgIhA8bVqk116W/bxB1Y4ZxAHTpy7QfQr5BrLZK TKTocu22ZbmErORACs3Phzy7Fbmz0UryFLnjYMOWaXInoE1tFuYw90Ql3osm4MpaSXYH gjHGpbYbhAyxEWtReU6owgPYSuNPitJn5Lznvxs/MyqtDvUIXp8FwIjBcWaz/hA0x2// YSg54m0QLkszZQKa36kbJvkG9sDD5x4M8jlikbBRCdU501I8CAvKPkb33vOtunidzzDy JV3g== X-Gm-Message-State: AOAM530IiApURnYjAGXo6L3liZgTGHvaUx3YpdYNI59WXf9a4I3Il8hx jiwUXZbPceFlJnst0+rTSNl+GsCCvXZScUT7EWoDFUYLEsY= X-Google-Smtp-Source: ABdhPJzYykjBSiVmL27ab31fUwRnxaDYtis2nWZvoO01AnaS07A8HHTYQ150SVwB2jTmh7GRJCR44dk7Yb0BC+Z4wEc= X-Received: by 2002:ac8:5b04:0:b0:306:6cea:18e2 with SMTP id m4-20020ac85b04000000b003066cea18e2mr4026105qtw.95.1655281851364; Wed, 15 Jun 2022 01:30:51 -0700 (PDT) MIME-Version: 1.0 References: <20220613132042.2972081-1-christoph.muellner@vrull.eu> <20220613132042.2972081-2-christoph.muellner@vrull.eu> In-Reply-To: <20220613132042.2972081-2-christoph.muellner@vrull.eu> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Wed, 15 Jun 2022 10:30:37 +0200 Message-ID: Subject: Re: [PATCH 2/2] riscv-cores.def: Add Allwinner D1 core To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Jun 2022 08:30:54 -0000 On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This adds Allwinner's D1 to the list of known cores. > The Allwinner includes a single-core XuanTie C906 and is available > for quite some time. Note, that the tuning struct for the C906 > is already part of GCC. > > gcc/ChangeLog: > > * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d1". > > Signed-off-by: Christoph M=C3=BCllner > --- > gcc/config/riscv/riscv-cores.def | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-co= res.def > index 60bcadbb034..dd97ece376f 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-s= eries") > RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") > RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") > > +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") I just realized that this lacks a test case (other -mcpu=3D... entries have= one). And the core string is wrong (s/thead-c906/allwinner-d1). I will send a v2. > + > #undef RISCV_CORE > -- > 2.35.3 >