From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by sourceware.org (Postfix) with ESMTPS id 4D1473858D20 for ; Wed, 15 May 2024 07:28:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4D1473858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4D1473858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::102b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715758120; cv=none; b=Qs6ducYJapEUGYRvv/CY/ttKo6Upz9kuuOejzByO988Lgi1IrhOarG6ncVdh1zGbiL5QSJKIet7CW0QzX/m1TxzMZ08VfZ1i1h6XDPeH+c6FxbNtjXPw17+H9IRkFwV4FmjmpKiVgqUHHV0SD5SuskKtnPf0J/oXTWka4y5cgNc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715758120; c=relaxed/simple; bh=u9LjdJclb2mwQbW0MGiQp2iq7UCBT4M0HfSNElCNzc4=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=Kqx5a1vFkNVyEL+4ATg5D0DZtILtRMt4VrpWIpO0HAlB2tpf4EJYPm7ttXN66mPQWSmv1DAn0OdEicI6j9Q3Yc1dLxLny2eYIweVzltsRNTXaU3L1zq+iNiGjH1MVMhrbFpxt1S927jSCUFGwvS6PHFk33x+PI8Am+noYrhfDQQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2b4952a1b51so5077175a91.0 for ; Wed, 15 May 2024 00:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1715758117; x=1716362917; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=QMz74z28dz9DiSUejXDfaDN+XzRoyOdBDquDx15hazU=; b=OhbDdfSdHtgCmRxjfBknRRJ9a8sGL6iWOpkzSuCYdZPSh402qnWT6MYXyjuR3HBlSl QGwYmGyXs78M6IEjWXBmaTa/g7lifBObh4rIS1haO1ah30jGjiSqaVn5FioCBmxZSGko rbxen4y9tMkNvtPTIyMXoY9e9WmLJ5RZJrLPbEeJrFWeyEmHD+7el5D++UHZAYIiMYAM vQL6JCP0gNcSZN494bXJGMA4bTFUWOk6Z4PFz5UBYPg7KW7UrWmDM95qgVWMmnYZbu2N x84eHJy9giQQeN1VWOpARCxZJxDbaa6uVxDJw6z0tnFm+QAulj9nX/QlUfog7kkMxMpX GaSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715758117; x=1716362917; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QMz74z28dz9DiSUejXDfaDN+XzRoyOdBDquDx15hazU=; b=luyAfOdjVDcnCBfXuQeWAQgrArQp+1h0gG8C18NDwaj4stQ3Ym8BfuYbL45Dbtdhbu lhhFTOXOO8raWt5//TikuWL0XddfW36tQvPzqeh3PAtjj9SL5bEb93DhCC+7pE8+d35i CevrEG8kuhWmr7SQuNB3Z/n71wSFNm7LcjOcld+3J15eSlVcmraVYYtzyvXG95GfA4CM 0Kov91qD6AWRFLw0FWVQX/266iq3mB/DCMOTzPD0Mb3O8BHKfWYQpYENVRv9mbEFWXuL T/5vFiBfm8oC3irDpqXrpBRLXq4Gj6WYka9MKvn9gKCSQ8ke8g/SQKqMaLeC05m6zQg6 7gug== X-Gm-Message-State: AOJu0YxVOzX8lxLsuwn+5VKWpKqZwro4JLDaXLh6HRliMYOGf0Zcinjt xFyaJCIe8h2wO6/HnIIHVQumTbKy7b2Qxu92ZUr+sOvcxgYqyY5uO21z4rwcpY7abY8jRzzrPyC ZvW09BW9+/L8+OGxogI7E8t3mnfbPMOf/ljUqhg== X-Google-Smtp-Source: AGHT+IHKeay0AVJf1W/caXFQmEpfJVIt9PVhT7dhq//9iyEwebu/xCA8XxjYOyLSIswrlJjPy9gpvetDZFlSmAVyAeo= X-Received: by 2002:a17:90b:3d1:b0:2a3:be59:e969 with SMTP id 98e67ed59e1d1-2b6ccef71b5mr10090074a91.47.1715758117195; Wed, 15 May 2024 00:28:37 -0700 (PDT) MIME-Version: 1.0 References: <20240515064841.2441351-1-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Wed, 15 May 2024 09:28:25 +0200 Message-ID: Subject: Re: [PATCH] RISC-V: Fix cbo.zero expansion for rv32 To: Kito Cheng Cc: gcc-patches@gcc.gnu.org, Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Vineet Gupta Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_NUMSUBJECT,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, May 15, 2024 at 9:14=E2=80=AFAM Kito Cheng = wrote: > > LGTM :) Jeff already committed a fix before, which also disables the test for rv32. I'll send up a follow-up patch to enable the test for rv32. > > On Wed, May 15, 2024 at 2:48=E2=80=AFPM Christoph M=C3=BCllner > wrote: > > > > Emitting a DI pattern won't find a match for rv32 and manifests in > > the failing test case gcc.target/riscv/cmo-zicboz-zic64-1.c. > > Let's fix this in the expansion and also address the different > > code that gets generated for rv32/rv64. > > > > gcc/ChangeLog: > > > > * config/riscv/riscv-string.cc (riscv_expand_block_clear_zicboz= _zic64b): > > Fix expansion for rv32. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32. > > > > Signed-off-by: Christoph M=C3=BCllner > > --- > > gcc/config/riscv/riscv-string.cc | 5 ++- > > .../gcc.target/riscv/cmo-zicboz-zic64-1.c | 36 ++++++------------- > > 2 files changed, 14 insertions(+), 27 deletions(-) > > > > diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-= string.cc > > index 87f5fdee3c1..b515f44d17a 100644 > > --- a/gcc/config/riscv/riscv-string.cc > > +++ b/gcc/config/riscv/riscv-string.cc > > @@ -827,7 +827,10 @@ riscv_expand_block_clear_zicboz_zic64b (rtx dest, = rtx length) > > { > > rtx mem =3D adjust_address (dest, BLKmode, offset); > > rtx addr =3D force_reg (Pmode, XEXP (mem, 0)); > > - emit_insn (gen_riscv_zero_di (addr)); > > + if (TARGET_64BIT) > > + emit_insn (gen_riscv_zero_di (addr)); > > + else > > + emit_insn (gen_riscv_zero_si (addr)); > > offset +=3D cbo_bytes; > > } > > > > diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c b/gcc/= testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c > > index c2d79eb7ae6..9192b391b11 100644 > > --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c > > +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c > > @@ -1,25 +1,9 @@ > > /* { dg-do compile } */ > > -/* { dg-options "-march=3Drv64gc_zic64b_zicboz" { target { rv64 } } } = */ > > /* { dg-options "-march=3Drv32gc_zic64b_zicboz" { target { rv32 } } } = */ > > +/* { dg-options "-march=3Drv64gc_zic64b_zicboz" { target { rv64 } } } = */ > > /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ > > -/* { dg-final { check-function-bodies "**" "" } } */ > > -/* { dg-allow-blank-lines-in-output 1 } */ > > > > -/* > > -**clear_buf_123: > > -** ... > > -** cbo\.zero\t0\(a[0-9]+\) > > -** sd\tzero,64\(a[0-9]+\) > > -** sd\tzero,72\(a[0-9]+\) > > -** sd\tzero,80\(a[0-9]+\) > > -** sd\tzero,88\(a[0-9]+\) > > -** sd\tzero,96\(a[0-9]+\) > > -** sd\tzero,104\(a[0-9]+\) > > -** sd\tzero,112\(a[0-9]+\) > > -** sh\tzero,120\(a[0-9]+\) > > -** sb\tzero,122\(a[0-9]+\) > > -** ... > > -*/ > > +// 1x cbo.zero, 7x sd (rv64) or 14x sw (rv32), 1x sh, 1x sb > > int > > clear_buf_123 (void *p) > > { > > @@ -27,17 +11,17 @@ clear_buf_123 (void *p) > > __builtin_memset (p, 0, 123); > > } > > > > -/* > > -**clear_buf_128: > > -** ... > > -** cbo\.zero\t0\(a[0-9]+\) > > -** addi\ta[0-9]+,a[0-9]+,64 > > -** cbo\.zero\t0\(a[0-9]+\) > > -** ... > > -*/ > > +// 2x cbo.zero, 1x addi 64 > > int > > clear_buf_128 (void *p) > > { > > p =3D __builtin_assume_aligned(p, 64); > > __builtin_memset (p, 0, 128); > > } > > + > > +/* { dg-final { scan-assembler-times "cbo\.zero\t" 3 } } */ > > +/* { dg-final { scan-assembler-times "addi\ta\[0-9\]+,a\[0-9\]+,64" 1 = } } */ > > +/* { dg-final { scan-assembler-times "sd\t" 7 { target { rv64 } } } } = */ > > +/* { dg-final { scan-assembler-times "sw\t" 14 { target { rv32 } } } }= */ > > +/* { dg-final { scan-assembler-times "sh\t" 1 } } */ > > +/* { dg-final { scan-assembler-times "sb\t" 1 } } */ > > -- > > 2.44.0 > >