From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by sourceware.org (Postfix) with ESMTPS id 0D60A3858D32 for ; Tue, 2 Jan 2024 19:51:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0D60A3858D32 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0D60A3858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::532 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704225063; cv=none; b=OvIrpU2Shuds83Scbae+JywBmijn5fuEWCXjZY73qQsfE0ACXKWM/FYwA3vcgn76FmWDjTA0Zx/jMYUX7zGDnk4lBWW0zZ3S5oJWumUOmiLhWZB8SDkarZw/0/V4ypmu/Gb10snUOHzkAK0y2spAp3XxgQnGwWpXhI4lsXXXie0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704225063; c=relaxed/simple; bh=iyvHKwgHA/4k7d5Qe4iCEMA9dSGpe67LGmWtIT22e54=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=dxf4IyjmPaPBv9KVSUwdNo26ls8Cx21Tt7B3x8bu57a2P4ivy9NNwelX5fVzBP9IaUqrANgXMZe2RSqkGXETXSjsFEDmkE5Izu4YL9U/N/yTlgHNu8b4OQMg77S8qUpCW+s4+gTaxIK4434aa+d0fXFnq5FbIfIDrYM4GZ//0rE= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-5cd5cdba609so7267377a12.0 for ; Tue, 02 Jan 2024 11:51:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1704225060; x=1704829860; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=JCEnwsVXEuxBbKe0CSi+iHHrFtLTSv9dwfimUMtyg7g=; b=K5HIYN7/HqyWjqbgPOmQnjtN93nL+Il76Uvs19CBM9TX6ZwIvlX417ZLBvCzxlArLm PP4TnW8ozcqbz+bIvMyvkaMt48femWHf2weTDB7KwLnNd9Av5VCEu0txi3PPsdj1/3oG zqiEm9/M6qq+HD0D60S3zbiG50rBlMU9f4L4SsKuVHy18lv77r8wzutgSKOpQROakXHp +4FX57xOkUb8K0wCXeC/bdA1is+nnqEPSGCwCTnrhzhkzynFSMpKC2zHnK3vZyxZO/Q2 eMC2pt0hcjgeVy+0v1y8zbrR5Z+nMnTP8SZw/Bv95pY3pVIObF7kn7XmB4cyE17tepHH Fs+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704225060; x=1704829860; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JCEnwsVXEuxBbKe0CSi+iHHrFtLTSv9dwfimUMtyg7g=; b=ciTWDXjyrm/NShizR1FBB4wxaEoPa0R3c/VoQiPJPfTigOwzZ5BgcWL+6H8TgXgD3X C7ccreZvqUegPnUrSf79tjTNA8EeZyfES983ZVTNhkGjmCRnytGZlcIHcTkhuj5phLez bMhJUGhA2rsiEvmI46Auwq+n3KhObQixhmsKAm7O97Tf9WOWFTUinDBroNoKFflSCBKI U8tqARZISZNU5Am6JkJtngkbyNO2Ir8t/wmptvsCUPw5XxO2SLg1bWd44gDvWC7wCUUj h+RzU223Stnt07QMoo7aK4pJl0PouqPF5r6secz7Wi+P1dESY4gkWl8KVh3w/CUxuptM sGFw== X-Gm-Message-State: AOJu0Yz7HegyhZ+buwnNXNhQWpsChx02XtE9qs/SbjQHtbWXE5/6V5fT E2j9jhjA6pmtfepUFpJzfpf26e4EjgU8Gdh97n7HY/QUatTXag== X-Google-Smtp-Source: AGHT+IEnoSejVnbB3lnYVVnsmbi1zKj+EnJv4w//7fqwRaUP8rasDsh39n5q1alAAptgd4hT/Q+/+5+9cdHUQiteKVw= X-Received: by 2002:a05:6a21:60a:b0:194:f6b3:d948 with SMTP id ll10-20020a056a21060a00b00194f6b3d948mr19664030pzb.16.1704225059922; Tue, 02 Jan 2024 11:50:59 -0800 (PST) MIME-Version: 1.0 References: <20231229040634.1153-1-cooper.joshua@linux.alibaba.com> <20231229041044.1206-1-cooper.joshua@linux.alibaba.com> <7616418DF2DD30D6+202401020935141666491@rivai.ai> In-Reply-To: <7616418DF2DD30D6+202401020935141666491@rivai.ai> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Tue, 2 Jan 2024 20:50:48 +0100 Message-ID: Subject: Re: [PATCH v4] RISC-V: Change csr_operand into vector_length_operand for vsetvl patterns. To: "juzhe.zhong@rivai.ai" Cc: "cooper.joshua" , gcc-patches , Jim Wilson , palmer , andrew , "philipp.tomsich" , jeffreyalaw , jinma , "cooper.qu" , Kito Cheng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Jan 2, 2024 at 2:35=E2=80=AFAM juzhe.zhong@rivai.ai wrote: > > LGTM assume you have passed the regression. Committed. I've rebased this patch, validated that there are no regressions with the p= atch, and reworded the commit message a bit before that. > > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Jun Sha (Joshua) > Date: 2023-12-29 12:10 > To: gcc-patches > CC: jim.wilson.gcc; palmer; andrew; philipp.tomsich; jeffreyalaw; christo= ph.muellner; juzhe.zhong; Jun Sha (Joshua); Jin Ma; Xianmiao Qu > Subject: [PATCH v4] RISC-V: Change csr_operand into vector_length_operand= for vsetvl patterns. > This patch use vector_length_operand instead of csr_operand for > vsetvl patterns, so that changes for vector will not affect scalar > patterns using csr_operand in riscv.md. > > gcc/ChangeLog: > > * config/riscv/vector.md: > Use vector_length_operand for vsetvl patterns. > > Co-authored-by: Jin Ma > Co-authored-by: Xianmiao Qu > Co-authored-by: Christoph M=C3=BCllner > --- > gcc/config/riscv/vector.md | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md > index f607d768b26..b5a9055cdc4 100644 > --- a/gcc/config/riscv/vector.md > +++ b/gcc/config/riscv/vector.md > @@ -1496,7 +1496,7 @@ > (define_insn "@vsetvl" > [(set (match_operand:P 0 "register_operand" "=3Dr") > - (unspec:P [(match_operand:P 1 "csr_operand" "rK") > + (unspec:P [(match_operand:P 1 "vector_length_operand" "rK") > (match_operand 2 "const_int_operand" "i") > (match_operand 3 "const_int_operand" "i") > (match_operand 4 "const_int_operand" "i") > @@ -1542,7 +1542,7 @@ > ;; in vsetvl instruction pattern. > (define_insn "@vsetvl_discard_result" > [(set (reg:SI VL_REGNUM) > - (unspec:SI [(match_operand:P 0 "csr_operand" "rK") > + (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK") > (match_operand 1 "const_int_operand" "i") > (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL)) > (set (reg:SI VTYPE_REGNUM) > @@ -1564,7 +1564,7 @@ > ;; such pattern can allow us gain benefits of these optimizations. > (define_insn_and_split "@vsetvl_no_side_effects" > [(set (match_operand:P 0 "register_operand" "=3Dr") > - (unspec:P [(match_operand:P 1 "csr_operand" "rK") > + (unspec:P [(match_operand:P 1 "vector_length_operand" "rK") > (match_operand 2 "const_int_operand" "i") > (match_operand 3 "const_int_operand" "i") > (match_operand 4 "const_int_operand" "i") > @@ -1608,7 +1608,7 @@ > [(set (match_operand:DI 0 "register_operand") > (sign_extend:DI > (subreg:SI > - (unspec:DI [(match_operand:P 1 "csr_operand") > + (unspec:DI [(match_operand:P 1 "vector_length_operand") > (match_operand 2 "const_int_operand") > (match_operand 3 "const_int_operand") > (match_operand 4 "const_int_operand") > -- > 2.17.1 > >