From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by sourceware.org (Postfix) with ESMTPS id 4F5D93858D35 for ; Wed, 22 Nov 2023 10:07:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4F5D93858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4F5D93858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::1036 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700647675; cv=none; b=d44nKH5+gJDyJAKKj6TsY6+q9px6CIqDT5cmF7FNLTsGBLQDQruUrNLnLdKZI58P6jXo2+oes05jUHR7Fn9154plS/zF5WdrX3oelxn3hGYANxHh87k1S/9Sa/Cs1a+6AYL+tPB9jPvKDnwCPM+jdYYi5CQH4/gA1uY6sP5xlcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700647675; c=relaxed/simple; bh=BFGka/gYFLCiieiVt9jrFg5u9WRVI3V7s5AA3kjUV2c=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=wF4T5pWZFSUFVBLqMwsb6Tq9uu1PNwibwJEHQv7QKJWAOH8Kb0bco1qDIcxw32gztT7CYihageeZI5QgZ1aU11uBUjIk12UkiJTmWq9OOx36BdJ/Mckdi3h4yVeFdqKBQ4TqRwgLIwI3XkxDtNInt/VdcI2yDexYtOUUcNIZE+k= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2853347502aso2106577a91.2 for ; Wed, 22 Nov 2023 02:07:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1700647671; x=1701252471; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=vCxjajW2tbg3XTt0V8v1c7gMT55RFqlepz75A6ILlb0=; b=tMBduRsTae7jpxn4nKvKJSqwCdTeaJ1mKo1lblsFeo0Xp5m+Ygo7wnLPOuHmr2s0f6 yymGY237A2mM6sfm4LFcVxhavSXMVy3zzdNx7p2/GIlJwuSbgHtHFeFhO6ygnxnMA4VE wPYvrY9z2SoSyyomTNGQ9JQRFoFn0hnc0GFPFcu1aLMN+5olb1xxwjHkVud0h+AdEvm0 OEm1jBT7yrdk01Rw/Er4PKlXM+zGb3ipApNS1a96HkBA/DGtYIeqr8wasG/TdPTv7mHc AK9Gasu4qM2CAUsald711opgUIWQ2DoD9iU2/taIKT/BtfZleKoPx/ZQx+mH4kRS3FmC Mr1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700647671; x=1701252471; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vCxjajW2tbg3XTt0V8v1c7gMT55RFqlepz75A6ILlb0=; b=r2ZcvaFBHXrVHz9lSPOTz95e/odx0NWm56yZe60IPhzhyczoa/thBwlitX0omeioaZ MC+YZB2P/q1/MCWKku59LLSeTV8JS6bk+gGLimBV2bs6GTU9j7Zo0qAnMRIqm/TYKncn /Fo6aVpTI8a2GezxXKTVj4g3/ecC0ehcydfiiPzzgWweIlGzs6XjkTw93hI65JlX7QU9 US/aPUa5uljZ9+lIq2NM8pn8N4mgNTdHS5v14qo5lPGyIAI8vthkKN890V96CrAvxI5M zmuvFy+lJITaJE6QjQceXOHk0VLeXTgRw/h8YdhiD4gnye/kuu+cB6Pl97JRm6UIX96H bgSQ== X-Gm-Message-State: AOJu0YzzYm/dVQ447hB03omC7YS4ycl+/lZ+VSITYESQ5sf9YqPtIp0x yXK6mq2cl6TNmY+wC4PCwSUoO1WFfsbgUm8ICk6EHQ== X-Google-Smtp-Source: AGHT+IFqAgQtQn/J2JQNHf1/3B4KUK4A9GoonaorUZOx22Jb7AgXN2CuVty/My6RAusrk12MrY4oQF82moqPRXL23Jk= X-Received: by 2002:a17:90a:187:b0:27d:3fa4:9d9a with SMTP id 7-20020a17090a018700b0027d3fa49d9amr1879844pjc.29.1700647671187; Wed, 22 Nov 2023 02:07:51 -0800 (PST) MIME-Version: 1.0 References: <202311171939484236058@rivai.ai> <799FFC52C75DBD19+2023111721411742145625@rivai.ai> In-Reply-To: <799FFC52C75DBD19+2023111721411742145625@rivai.ai> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Wed, 22 Nov 2023 11:07:37 +0100 Message-ID: Subject: Re: RISC-V: Support XTheadVector extensions To: "juzhe.zhong@rivai.ai" Cc: gcc-patches , "kito.cheng" , "Kito.cheng" , "cooper.joshua" , Robin Dapp , jeffreyalaw , Philipp Tomsich , Cooper Qu , Jin Ma , Nelson Chu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Juzhe, Sorry for the late reply, but I was not on CC, so I missed this email. On Fri, Nov 17, 2023 at 2:41=E2=80=AFPM juzhe.zhong@rivai.ai wrote: > > Ok. I just read the theadvector extension. > > https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadvec= tor.adoc > > Theadvector is not custom extension. Just a uarch to disable some of the = RVV1.0 extension > Theadvector can be considered as subextension of 'V' extension with disab= ling some of the > instructions and adding some new thead vector target load/store (This is = another story). > > So, for disabling the instruction that theadvector doesn't support. > You don't need to touch such many codes. > > Here is a much simpler approach to do (I think it's definitely working): > 1. Don't change any codes in vector.md and keep GCC generates ASM with "t= h." prefix. > 2. Add !TARGET_THEADVECTOR into vector-iterator.md to disable the mode yo= u don't want. > For example , theadvector doesn't support fractional vector. > > Then it's pretty simple: > > RVVMF2SI "TARGET_VECTOR && !TARGET_THEADVECTOR". > > 3. Remove all the tests you add in this patch. > 4. You can add theadvector specific load/store for example, th.vlb instru= ctions they are allowed. > 5. Modify binutils, and make th.vmulh.vv as the pseudo instruction of vmu= lh.vv > 6. So with compile option "-S", you will still see ASM as "vmulh.vv". bu= t with objdump, you will see th.vmulh.vv. Yes, all these points sound reasonable, to minimize the patchset size. I believe in point 1 you meant "without th. prefix". I've added Jin Ma (who is the main author of the Binutils patchset) so he is also aware of the proposal to use pseudo instructions to avoid duplication in Binutils= . Thank you very much! Christoph > > After this change, you can send V2, then I can continue to review on GCC-= 15. > > Thanks. > > ________________________________ > juzhe.zhong@rivai.ai > > > From: juzhe.zhong@rivai.ai > Date: 2023-11-17 19:39 > To: gcc-patches > CC: kito.cheng; kito.cheng; cooper.joshua; Robin Dapp; jeffreyalaw > Subject: RISC-V: Support XTheadVector extensions > 90% theadvector extension reusing current RVV 1.0 instructions patterns: > Just change ASM, For example: > > @@ -2923,7 +2923,7 @@ (define_insn "*pred_mulh_scalar" > (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMU= LH) > (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))] > "TARGET_VECTOR" > - "vmulh.vx\t%0,%3,%z4%p1" > + "%^vmulh.vx\t%0,%3,%z4%p1" > [(set_attr "type" "vimul") > (set_attr "mode" "")]) > > + if (letter =3D=3D '^') > + { > + if (TARGET_XTHEADVECTOR) > + fputs ("th.", file); > + return; > + } > > > For almost all patterns, you just simply append "th." in the ASM prefix. > like change "vmulh.vv" -> "th.vmulh.vv" > > Almost all theadvector instructions are not new features, all same as RV= V1.0. > Why do you invent the such ISA doesn't include any features that RVV1.0 d= oesn't satisfy ? > > I am not explicitly object this patch. But I should know the reason. > > Btw, stage 1 will close soon. So I will review this patch on GCC-15 as l= ong as all other RISC-V maintainers agree. > > > ________________________________ > juzhe.zhong@rivai.ai