From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id A88773858CDA for ; Wed, 2 Nov 2022 14:21:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A88773858CDA Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-pl1-x634.google.com with SMTP id y4so16736405plb.2 for ; Wed, 02 Nov 2022 07:21:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=fUk+5q+lXlAn5R5JstDl+eIjtGvbuABrROvG7M3dW1o=; b=hmX6bzAru0tqkVReCysilKbq7w9M+ZnvWXTEwK+mT++Jj5Wa2WBUey/e1LDh/i/dXa hwkmVy7y31vuVlPqpQQvSz1dG9ZJ7dU7120BmYRL3qt7Q+Aid1CJuqWru43Q9VYyBSaC NIxkwzKkpv0fYhKPvlt26wRrL41dPb+j7vAjAbtpQDopKX7kt4zGvNejL3xhWdcw3zuC 2ZLtvWt2lbX3lG0A3T+Txw6EjG3mSBGW4vCM/wty8xAKgF6F+uPcvOdQ3JW2TOknUT9l SxoJ/9H7azX8/6lPaU3RLp1m2xiwGH1nxrSC5xWpOQqiCPMqDjuIpbqvRXnfQRNXWQ/0 Q50A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=fUk+5q+lXlAn5R5JstDl+eIjtGvbuABrROvG7M3dW1o=; b=k15bAIEjOHXfhulj0vK4rj9p7ON8y3A1eZkRS6Ol7AEvUw32RrASyiLDagoZ/WEtkc uwdm5+SQBK/N5nsALLJNrSGI0aR6JkwRiT8QbV2xpkG/lVl3LpMOglkpxyvbnhOdv6JI OYZ7BX1Oi7EbJLXL4QP/UypLS8Y7r9svljvltaqtdDJ1zOpnwW7SwVFYUm1y9G7YHfdc MEXg2fKkMfnHemB6BfviZ+dx5ZzZgIwklHeFI3UyFUZvIytKot/Zrvj6L5jJ9VPEVXH6 CioRsarSmXn/TUXq1HUiTmnZuMxH2HXFHCPKQ03xJAB0rDCbMEbjcBZosPGfF01f5dT/ FWVw== X-Gm-Message-State: ACrzQf1TuFSGANyKGnjhmllq9KI5le5q1bga1DzQHI/0roW71eSRDxEX tjz8FT7T3HVy5QJFSH06061HtqIyVP5jfLGpoAlxRA== X-Google-Smtp-Source: AMsMyM4/PdtnEHpisnACKbu06AlXMz8f71mrMvf/Y2ZDi6Wa056f4pINfSy4bYKYMr1o/QGlV/tdXR4MCaxFAkI1DJo= X-Received: by 2002:a17:90b:4d82:b0:214:1066:921c with SMTP id oj2-20020a17090b4d8200b002141066921cmr9303295pjb.230.1667398867590; Wed, 02 Nov 2022 07:21:07 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Wed, 2 Nov 2022 15:20:56 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Add Zawrs ISA extension support To: Palmer Dabbelt Cc: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com, Jim Wilson , Andrew Waterman , philipp.tomsich@vrull.eu, jeffreyalaw@gmail.com, Aaron Durbin , Vineet Gupta Content-Type: multipart/alternative; boundary="00000000000033b3d505ec7d8d31" X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,HTML_MESSAGE,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --00000000000033b3d505ec7d8d31 Content-Type: text/plain; charset="UTF-8" On Thu, Oct 27, 2022 at 10:51 PM Palmer Dabbelt wrote: > On Thu, 27 Oct 2022 11:23:17 PDT (-0700), christoph.muellner@vrull.eu > wrote: > > On Thu, Oct 27, 2022 at 8:11 PM Christoph Muellner < > > christoph.muellner@vrull.eu> wrote: > > > >> From: Christoph Muellner > >> > >> This patch adds support for the Zawrs ISA extension. > >> The patch depends on the corresponding Binutils patch > >> to be usable (see [1]) > >> > >> The specification can be found here: > >> https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > >> > >> Note, that the Zawrs extension is not frozen or ratified yet. > >> Therefore this patch is an RFC and not intended to get merged. > >> > > > > Sorry, forgot to update this part: > > The Zawrs extension is frozen but not ratified. > > Let me know if I should send a v2 for this change of the commit msg. > > IMO it's fine to just fix it up at commit time. This LGTM, we just need > the NEWS entry too. I also don't see any build/test results. > I ran the GCC regression test suite with rv32 and rv64 toolchains using the riscv-gnu-toolchain repo and did not see any regressions. Where can I create the news entry? > > Thanks! > > > Binuitls support has been merged recently: > > > > > https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=eb668e50036e979fb0a74821df4eee0307b44e66 > > > > > >> > >> [1] https://sourceware.org/pipermail/binutils/2022-April/120559.html > >> > >> gcc/ChangeLog: > >> > >> * common/config/riscv/riscv-common.cc: Add zawrs extension. > >> * config/riscv/riscv-opts.h (MASK_ZAWRS): New. > >> (TARGET_ZAWRS): New. > >> * config/riscv/riscv.opt: New. > >> > >> gcc/testsuite/ChangeLog: > >> > >> * gcc.target/riscv/zawrs.c: New test. > >> > >> Signed-off-by: Christoph Muellner > >> --- > >> gcc/common/config/riscv/riscv-common.cc | 4 ++++ > >> gcc/config/riscv/riscv-opts.h | 3 +++ > >> gcc/config/riscv/riscv.opt | 3 +++ > >> gcc/testsuite/gcc.target/riscv/zawrs.c | 13 +++++++++++++ > >> 4 files changed, 23 insertions(+) > >> create mode 100644 gcc/testsuite/gcc.target/riscv/zawrs.c > >> > >> diff --git a/gcc/common/config/riscv/riscv-common.cc > >> b/gcc/common/config/riscv/riscv-common.cc > >> index d6404a01205..4b7f777c103 100644 > >> --- a/gcc/common/config/riscv/riscv-common.cc > >> +++ b/gcc/common/config/riscv/riscv-common.cc > >> @@ -163,6 +163,8 @@ static const struct riscv_ext_version > >> riscv_ext_version_table[] = > >> {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, > >> {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, > >> > >> + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, > >> + > >> {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, > >> {"zbb", ISA_SPEC_CLASS_NONE, 1, 0}, > >> {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, > >> @@ -1180,6 +1182,8 @@ static const riscv_ext_flag_table_t > >> riscv_ext_flag_table[] = > >> {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, > >> {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, > >> > >> + {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, > >> + > >> {"zba", &gcc_options::x_riscv_zb_subext, MASK_ZBA}, > >> {"zbb", &gcc_options::x_riscv_zb_subext, MASK_ZBB}, > >> {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, > >> diff --git a/gcc/config/riscv/riscv-opts.h > b/gcc/config/riscv/riscv-opts.h > >> index 1dfe8c89209..25fd85b09b1 100644 > >> --- a/gcc/config/riscv/riscv-opts.h > >> +++ b/gcc/config/riscv/riscv-opts.h > >> @@ -73,6 +73,9 @@ enum stack_protector_guard { > >> #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) > >> #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) > >> > >> +#define MASK_ZAWRS (1 << 0) > >> +#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0) > >> + > >> #define MASK_ZBA (1 << 0) > >> #define MASK_ZBB (1 << 1) > >> #define MASK_ZBC (1 << 2) > >> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > >> index 426ea95cd14..7c3ca48d1cc 100644 > >> --- a/gcc/config/riscv/riscv.opt > >> +++ b/gcc/config/riscv/riscv.opt > >> @@ -203,6 +203,9 @@ long riscv_stack_protector_guard_offset = 0 > >> TargetVariable > >> int riscv_zi_subext > >> > >> +TargetVariable > >> +int riscv_za_subext > >> + > >> TargetVariable > >> int riscv_zb_subext > >> > >> diff --git a/gcc/testsuite/gcc.target/riscv/zawrs.c > >> b/gcc/testsuite/gcc.target/riscv/zawrs.c > >> new file mode 100644 > >> index 00000000000..0b7e2662343 > >> --- /dev/null > >> +++ b/gcc/testsuite/gcc.target/riscv/zawrs.c > >> @@ -0,0 +1,13 @@ > >> +/* { dg-do compile } */ > >> +/* { dg-options "-march=rv64gc_zawrs" { target { rv64 } } } */ > >> +/* { dg-options "-march=rv32gc_zawrs" { target { rv32 } } } */ > >> + > >> +#ifndef __riscv_zawrs > >> +#error Feature macro not defined > >> +#endif > >> + > >> +int > >> +foo (int a) > >> +{ > >> + return a; > >> +} > >> -- > >> 2.37.3 > >> > >> > --00000000000033b3d505ec7d8d31--