From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by sourceware.org (Postfix) with ESMTPS id 7E2C73858D32 for ; Fri, 10 Nov 2023 13:30:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7E2C73858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7E2C73858D32 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::42b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699623060; cv=none; b=H4zeYDzRbuYSNSx0aJ55P+06xzkwJXSfyjUisBW/IiluUkutOM5N7/V8lX2W8Jde//tw9IKbhAiJiZJZNHbMz+kF4InMc95rSFmYA1ypG6qLw7HSZkiaGTp3UZE5aosNlJdBzodAq7vxt+uLpEWR8xoylOg0BNfXvZShrd/YhhM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699623060; c=relaxed/simple; bh=owXmY4CQmGJJpgBFc3N6W5XUoSbWqBeKE289txzx/fo=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=EiDXb7jqm8ZPXbpTkmmKZp6oOYL95gmFKJZPG3I5QL7yFKLsICURhOYQn20kNqQGzd2BbUgkRXMe1N8d7q3XRzYFgB7YLAFNTmISrnXbjFL7UYlWY9btDrxMCCD1Hw9iFJqr+ySwharAWa+w5S5Xk8z31UpG2T/AVjjImymo9tU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6c431ca7826so1937431b3a.0 for ; Fri, 10 Nov 2023 05:30:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1699623057; x=1700227857; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=8kO/vv60+3DpjSzuoSagsVMMNV5bSJbV8qzc1Ku8LFU=; b=G7BaFJIfSo54k0s0+kq7hICwqQX2XQXCPcnEDGdaOvTu3zhwonUhQwssKTEJN5sNUD +Vziz8TJAEsOqLlB+jiZtypy/gpYVy077x4onfcLi2tqsKEeqFAnPRDCdKOy2hufgSwZ 1S1xrp0mRXDzCW8eVMbYmkDu9EqM/DJmQuzyCH6TivKrMqqB//JxAYjsDkxyEPDJObHq BYR+K+0pF1Rq0ci12foZyVW6X8Qr/uSpn278DT3NckHoswPf7nd5HW6XwbP8wMT0IHag 8nHb5onfVt4LJIXvdpFsTUF7bt6K8eIEmk0BYuvnZIEK0OFKgAem6TQVft2IgZUTtW7j LwFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699623057; x=1700227857; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8kO/vv60+3DpjSzuoSagsVMMNV5bSJbV8qzc1Ku8LFU=; b=TMF+wrD2+HYw+Sda1zhi2oCqAOt90JbVlxwgOBGylvLfa+NZ1Km52thFbje5ne/TGT boLrtwKVFb43ek422IgPl4dQjoxMuEUP5v3qjJWFAEpu1PU0VO6wxSNZ9LE1witSJg0I utZSvJa2Tq12o28IWLtn0AMEll1BbVfi+WoY9Wbj30Acb/HgxzuxQS1ix7XdTW5QNlBS FUn+BJsZzKX2SuWIaAkhPrDnbtPkhqf/U0XrKFI0lS6NgtXFs0+MhZPo7RVefrAFMWBs +DznTHq3vZsM73q9V5Ym0uGek173yHs3PyyOwSU4aMVAGKk5yyYPfhPEt2TEtQZ6TMQh dUTA== X-Gm-Message-State: AOJu0YzrAFa7KIxB89azs40RcL7AWNUi7bKYDEXrbJMvF6BW5KA6wjak bvnFVW/pLahBrwPBZ7cFVuNRTxadUxXMS2oyphryawz46Df7ZpAJ X-Google-Smtp-Source: AGHT+IGAf8flf9lb8nV2ec/wkjZWhaHsHp7kum56ATsGMu4fKsT96SHQ6SSCAHhCtyxHD23jF9uCFWpikdN4SdYI4XI= X-Received: by 2002:a05:6a20:8417:b0:181:16c7:6cd0 with SMTP id c23-20020a056a20841700b0018116c76cd0mr10029628pzd.17.1699623057253; Fri, 10 Nov 2023 05:30:57 -0800 (PST) MIME-Version: 1.0 References: <20231110071431.1580-1-jinma@linux.alibaba.com> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Fri, 10 Nov 2023 14:30:45 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Fix bug that XTheadMemPair extension caused fcsr not to be saved and restored before and after interrupt. To: Kito Cheng Cc: Jin Ma , gcc-patches@gcc.gnu.org, jinma.contrib@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Nov 10, 2023 at 2:20=E2=80=AFPM Kito Cheng w= rote: > > LGTM Committed after shortening the commit message's heading. > > Christoph M=C3=BCllner =E6=96=BC 2023=E5=B9= =B411=E6=9C=8810=E6=97=A5 =E9=80=B1=E4=BA=94=EF=BC=8C20:55=E5=AF=AB=E9=81= =93=EF=BC=9A >> >> On Fri, Nov 10, 2023 at 8:14=E2=80=AFAM Jin Ma = wrote: >> > >> > The t0 register is used as a temporary register for interrupts, so it = needs >> > special treatment. It is necessary to avoid using "th.ldd" in the inte= rrupt >> > program to stop the subsequent operation of the t0 register, so they n= eed to >> > exchange positions in the function "riscv_for_each_saved_reg". >> >> RISCV_PROLOGUE_TEMP_REGNUM needs indeed to be treated special >> in case of ISRs and fcsr. This patch just moves the TARGET_XTHEADMEMPAIR >> block after the ISR/fcsr block. >> >> Reviewed-by: Christoph M=C3=BCllner >> >> > >> > gcc/ChangeLog: >> > >> > * config/riscv/riscv.cc (riscv_for_each_saved_reg): Place the = interrupt >> > operation before the XTheadMemPair. >> > --- >> > gcc/config/riscv/riscv.cc | 56 +++++++++---------= - >> > .../riscv/xtheadmempair-interrupt-fcsr.c | 18 ++++++ >> > 2 files changed, 46 insertions(+), 28 deletions(-) >> > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-inter= rupt-fcsr.c >> > >> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc >> > index e25692b86fc..fa2d4d4b779 100644 >> > --- a/gcc/config/riscv/riscv.cc >> > +++ b/gcc/config/riscv/riscv.cc >> > @@ -6346,6 +6346,34 @@ riscv_for_each_saved_reg (poly_int64 sp_offset,= riscv_save_restore_fn fn, >> > && riscv_is_eh_return_data_register (regno)) >> > continue; >> > >> > + /* In an interrupt function, save and restore some necessary CS= Rs in the stack >> > + to avoid changes in CSRs. */ >> > + if (regno =3D=3D RISCV_PROLOGUE_TEMP_REGNUM >> > + && cfun->machine->interrupt_handler_p >> > + && ((TARGET_HARD_FLOAT && cfun->machine->frame.fmask) >> > + || (TARGET_ZFINX >> > + && (cfun->machine->frame.mask & ~(1 << RISCV_PROLOGU= E_TEMP_REGNUM))))) >> > + { >> > + unsigned int fcsr_size =3D GET_MODE_SIZE (SImode); >> > + if (!epilogue) >> > + { >> > + riscv_save_restore_reg (word_mode, regno, offset, fn); >> > + offset -=3D fcsr_size; >> > + emit_insn (gen_riscv_frcsr (RISCV_PROLOGUE_TEMP (SImode)= )); >> > + riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGN= UM, >> > + offset, riscv_save_reg); >> > + } >> > + else >> > + { >> > + riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGN= UM, >> > + offset - fcsr_size, riscv_restor= e_reg); >> > + emit_insn (gen_riscv_fscsr (RISCV_PROLOGUE_TEMP (SImode)= )); >> > + riscv_save_restore_reg (word_mode, regno, offset, fn); >> > + offset -=3D fcsr_size; >> > + } >> > + continue; >> > + } >> > + >> > if (TARGET_XTHEADMEMPAIR) >> > { >> > /* Get the next reg/offset pair. */ >> > @@ -6376,34 +6404,6 @@ riscv_for_each_saved_reg (poly_int64 sp_offset,= riscv_save_restore_fn fn, >> > } >> > } >> > >> > - /* In an interrupt function, save and restore some necessary CS= Rs in the stack >> > - to avoid changes in CSRs. */ >> > - if (regno =3D=3D RISCV_PROLOGUE_TEMP_REGNUM >> > - && cfun->machine->interrupt_handler_p >> > - && ((TARGET_HARD_FLOAT && cfun->machine->frame.fmask) >> > - || (TARGET_ZFINX >> > - && (cfun->machine->frame.mask & ~(1 << RISCV_PROLOGU= E_TEMP_REGNUM))))) >> > - { >> > - unsigned int fcsr_size =3D GET_MODE_SIZE (SImode); >> > - if (!epilogue) >> > - { >> > - riscv_save_restore_reg (word_mode, regno, offset, fn); >> > - offset -=3D fcsr_size; >> > - emit_insn (gen_riscv_frcsr (RISCV_PROLOGUE_TEMP (SImode)= )); >> > - riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGN= UM, >> > - offset, riscv_save_reg); >> > - } >> > - else >> > - { >> > - riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGN= UM, >> > - offset - fcsr_size, riscv_restor= e_reg); >> > - emit_insn (gen_riscv_fscsr (RISCV_PROLOGUE_TEMP (SImode)= )); >> > - riscv_save_restore_reg (word_mode, regno, offset, fn); >> > - offset -=3D fcsr_size; >> > - } >> > - continue; >> > - } >> > - >> > riscv_save_restore_reg (word_mode, regno, offset, fn); >> > } >> > >> > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmempair-interrupt-fc= sr.c b/gcc/testsuite/gcc.target/riscv/xtheadmempair-interrupt-fcsr.c >> > new file mode 100644 >> > index 00000000000..d06f05f5c7c >> > --- /dev/null >> > +++ b/gcc/testsuite/gcc.target/riscv/xtheadmempair-interrupt-fcsr.c >> > @@ -0,0 +1,18 @@ >> > +/* Verify that fcsr instructions emitted. */ >> > +/* { dg-do compile } */ >> > +/* { dg-require-effective-target hard_float } */ >> > +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-g" "-Oz" "-Os" "-flto" }= } */ >> > +/* { dg-options "-march=3Drv64gc_xtheadmempair -mtune=3Dthead-c906 -f= unwind-tables" { target { rv64 } } } */ >> > +/* { dg-options "-march=3Drv32gc_xtheadmempair -mtune=3Dthead-c906 -f= unwind-tables" { target { rv32 } } } */ >> > + >> > + >> > +extern int foo (void); >> > + >> > +void __attribute__ ((interrupt)) >> > +sub (void) >> > +{ >> > + foo (); >> > +} >> > + >> > +/* { dg-final { scan-assembler-times "frcsr\t" 1 } } */ >> > +/* { dg-final { scan-assembler-times "fscsr\t" 1 } } */ >> > >> > base-commit: e7f4040d9d6ec40c48ada940168885d7dde03af9 >> > -- >> > 2.17.1 >> >