From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by sourceware.org (Postfix) with ESMTPS id 07615385840A for ; Thu, 9 Nov 2023 08:08:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 07615385840A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 07615385840A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::434 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699517300; cv=none; b=ZhCkOyzTiXb780f5rb90lpz40FL3gRD7SKIFgHAYNkvCs+wEXZFsvxEB04aJ8O4AcSc8hNOtuMR5iDNju4NYpAm8G8J7/O+OOAUeigzQmTJFEMUi2SitVQPgGlNTOvH1M6g6gvgeUa11MfZdaYjZIGhb9D7Qxb8UcE2uLt5272c= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699517300; c=relaxed/simple; bh=84+KDQ9uKvMKELfFlGziZNjRB+jKytztyR6lViQdgNE=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=Qn8qri0DkX2p9kVM/sAMEBlRHbWtVFcVn2o542iNr0sTRvIkwQ6xghK2LxPWp9qVpIfF1nYoGV2mwvMfj7aA/LQ7w7aTcT8U2Jijqo0qqt71pNuw6Y0rksEXzHQnmoK16ldhyt/XH8nU2T6JEeEkn5yPaHYq4UfEcxLr7vuO2/8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-6c10f098a27so521863b3a.2 for ; Thu, 09 Nov 2023 00:08:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1699517298; x=1700122098; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=ocSCXLarDi1wHN3U8ABSp8zcO7xMwFIua+ozDzB8nIM=; b=IawTBdYeRypZH+RN6ce1FNgRQ0AGCA/Z5ufq/gfKiHEsB8xgOit1AXTJjwDAqJHaM2 jVYO67F5k8DqFgiN1bQ7BALHjoZd/+uQNcb/1kOgtueWXEIxngAN7oibiLJddIWMkLYK VWw/8iMAJ7BY7oW9yrlAocA+AIA/983R2gR7qp+Cj3mvHR/3NqZcH3rPV2Fn95nk72E1 PESjBPUljnmAISjn/pC6u/Qs27UgPjYas90oHljNfMK21kXRXI/OADnxPp39WVfL2dQA eQYwWekaYfIcE6iPrPjyKdVRxSQSTdmqN00D8gB/wqb+nDa6zJ7AtyfuIw5UowK0tigZ Cijg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699517298; x=1700122098; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ocSCXLarDi1wHN3U8ABSp8zcO7xMwFIua+ozDzB8nIM=; b=l/LgA3mPn1WF8xe8HrI60vmrtQH66jPhHGbLNq8lNmjvMjGca33TNkenzAPaTwP92s y5PDB1vu9FrwcV5op/pNHGSEewEurcNTQ5fqrLu7Xh8VvoVGJXWT7Dr4eegqqszvzYYd 5CXRpF6eykoI8X8QoAmHzxIz53AyeapqoFsLNFEtLigXsESClZ7/E8Ha49wIAN7Hzc6+ kyKBh4G2hxQXA5lxTiBEX3Ve5N8Nb/Aq6w+81+8Pj+kLDDAeravdEFdRwFKkGSREztRU 27X4xHfFzpxeWIbHWvZerlcYXnyLmXnUXqiCuOjpGewul8XWjsGp5JNnezsvKo/ue7ET Ukgg== X-Gm-Message-State: AOJu0YzF5pSm3Z8gKdYaRlfuA3chrvBzkRawqCnid3rPAWe+FoG8G0yQ M0mxt9bfO5RtonSb7x1vraNvFOfYO4B7pyFgY9Fz1L55nFjcCf0x X-Google-Smtp-Source: AGHT+IFCHGo27Nh7bZewXQ/2Ar9sV9dmolcKcmuEkO7cUI9oVPZebpNlYpZGXgZ2VFsLvJyIIBveaVNTkDyZQHgpF4Q= X-Received: by 2002:a05:6a20:3956:b0:17a:eddb:ac65 with SMTP id r22-20020a056a20395600b0017aeddbac65mr4736381pzg.9.1699517298012; Thu, 09 Nov 2023 00:08:18 -0800 (PST) MIME-Version: 1.0 References: <20231109074008.580-1-jinma@linux.alibaba.com> In-Reply-To: <20231109074008.580-1-jinma@linux.alibaba.com> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Thu, 9 Nov 2023 09:08:04 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Fix the illegal operands for the XTheadMemidx extension. To: Jin Ma Cc: gcc-patches@gcc.gnu.org, jinma.contrib@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Nov 9, 2023 at 8:40=E2=80=AFAM Jin Ma wro= te: > > The pattern "*extend2_bitmanip" and > "*zero_extendhi2_bitmanip" in bitmanip.md are similar > to the pattern "*th_memidx_bb_extendqi2" and > "*th_memidx_bb_zero_extendhi2" in thead.md, which will > cause the wrong instruction to be generated and report the > following error in binutils: > Assembler messages: > Error: illegal operands `lb a5,(a0),1,0' > > In fact, the correct instruction is "th.lbia a5,(a0),1,0". LGTM. This zbb_xtheadmemidx was not part of the test matrix. We only had xtheadbb_xtheadmemidx there. Thanks! > > gcc/ChangeLog: > > * config/riscv/bitmanip.md: Avoid the conflict between > zbb and xtheadmemidx in patterns. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/xtheadfmemidx-uindex-zbb.c: New test. > --- > gcc/config/riscv/bitmanip.md | 4 +-- > .../riscv/xtheadfmemidx-uindex-zbb.c | 30 +++++++++++++++++++ > 2 files changed, 32 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-z= bb.c > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md > index a9c8275fca7..878395c3ffa 100644 > --- a/gcc/config/riscv/bitmanip.md > +++ b/gcc/config/riscv/bitmanip.md > @@ -290,7 +290,7 @@ (define_insn "*di2" > (define_insn "*zero_extendhi2_bitmanip" > [(set (match_operand:GPR 0 "register_operand" "=3Dr,r") > (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "r,m= ")))] > - "TARGET_ZBB" > + "TARGET_ZBB && !TARGET_XTHEADMEMIDX" > "@ > zext.h\t%0,%1 > lhu\t%0,%1" > @@ -301,7 +301,7 @@ (define_insn "*extend2_bitm= anip" > [(set (match_operand:SUPERQI 0 "register_operand" "=3Dr,r") > (sign_extend:SUPERQI > (match_operand:SHORT 1 "nonimmediate_operand" " r,m")))] > - "TARGET_ZBB" > + "TARGET_ZBB && !TARGET_XTHEADMEMIDX" > "@ > sext.\t%0,%1 > l\t%0,%1" > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c b/= gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c > new file mode 100644 > index 00000000000..a05bc220cba > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-uindex-zbb.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ > +/* { dg-options "-march=3Drv64gc_zbb_xtheadmemidx -mabi=3Dlp64d" { targe= t { rv64 } } } */ > +/* { dg-options "-march=3Drv32imafc_zbb_xtheadmemidx -mabi=3Dilp32f" { t= arget { rv32 } } } */ > + > +const unsigned char * > +read_uleb128(const unsigned char *p, unsigned long *val) > +{ > + unsigned int shift =3D 0; > + unsigned char byte; > + unsigned long result; > + > + result =3D 0; > + do > + { > + byte =3D *p++; > + result |=3D ((unsigned long)byte & 0x7f) << shift; > + shift +=3D 7; > + } while (byte & 0x80); > + > + *val =3D result; > + return p; > +} > + > +void test(const unsigned char *p, unsigned long utmp) > +{ > + p =3D read_uleb128(p, &utmp); > +} > + > +/* { dg-final { scan-assembler-not {\mlb\ta[0-9],\(a[0-9]\),1,0\M} } } *= / > > base-commit: 04d8a47608dcae7f61805e3566e3a1571b574405 > -- > 2.17.1 >