Re: [PATCH v2 4/4] RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4

["Christoph Müllner" <christoph.muellner@vrull.eu>]

On Wed, May 8, 2024 at 3:48 PM Jeff Law <jeffreyalaw@gmail.com> wrote:
>
>
>
> On 5/8/24 1:36 AM, Christoph Müllner wrote:
> > The lshr<GPR:mode>3_zero_extend_4 pattern targets bit extraction
> > with zero-extension. This pattern represents the canonical form
> > of zero-extensions of a logical right shift.
> >
> > The same optimization can be applied to sign-extensions.
> > Given the two optimizations are so similar, this patch converts
> > the existing one to also cover the sign-extension case as well.
> >
> > gcc/ChangeLog:
> >
> >       * config/riscv/iterators.md (ashiftrt): New code attribute
> >       'extract_shift' and adding extractions to optab.
> >       * config/riscv/riscv.md (*lshr<GPR:mode>3_zero_extend_4): Rename to...
> >       (*<any_extract:optab><GPR:mode>3):...this and add support for
> >       sign-extensions.
> >
> > gcc/testsuite/ChangeLog:
> >
> >       * gcc.target/riscv/extend-shift-helpers.h: Add helpers for
> >       sign-extension.
> >       * gcc.target/riscv/sign-extend-rshift-32.c: New test.
> >       * gcc.target/riscv/sign-extend-rshift-64.c: New test.
> >       * gcc.target/riscv/sign-extend-rshift.c: New test.
> Oh, I see, you handled the special case with this patch.  Ignore my
> comment on 3/4.  3/4 is fine, as is this patch.

Oh, yes, I forgot to add this to 3/4.

Thanks!

>
> Thanks!
>
> jeff