From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by sourceware.org (Postfix) with ESMTPS id 5217C385840F for ; Fri, 24 Feb 2023 11:27:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5217C385840F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-pf1-x42b.google.com with SMTP id ay18so1573847pfb.2 for ; Fri, 24 Feb 2023 03:27:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=6Uv8kMfmLSl+Dap1UGALxaBWWj9u4UzAbZ9WqgFbYOs=; b=JHTgIyEVA3IZAdDv8oPHxnhc00M+fSvFOxdwtRGV5Na424ILeTmsA2W4DaoelUqhO2 mTlR7rblQ+zFeL1OB+Z61PPreMAebzhEwiMMtgKaG8HXkMbjSNcXe6pX2+Q8CNbZqDhD ZBQBzfsNNe45RQZvw7XTfJ0rnOYkte80GhvTsd1p+EJ89fNInsn14LnbQn8/LDhBpgNl 9mJiaTb3b7gsDnNmh6PpCbyr4xg+thsaTTVkhpDuEKFjQ3Yta9GbV0ro/55SRX3UzQM/ U3r/M6Z0RROLQprOBpCPco2z8mHs4aKOWJZOVV4R50Jgw8KXIbDYkHOvm1HlhtsRLKT0 wuuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Uv8kMfmLSl+Dap1UGALxaBWWj9u4UzAbZ9WqgFbYOs=; b=xNPudDnsIlfzfyTvGFPOUKch+q1NvhMjwzU7TFQHrQ6zPp6n1P6fI5qUapQ3oTdu4B 4p7CqROIrpiuR9zvM62imSM130XFAnvIz7dW72EygloFYG2aJlhvbf7sefV02uimZIE+ wKpKMRFdcFJFunO2eJ4Ur+YOyyoEQm4R4XlUVF06bDdxVTNMi2R+WOlF0Rg2QaBpPdtF 6c+eCpoTfBG9V76/BtJI1rFOUOpP38OENZy0/0H6H+Xdbo1oXZG0cQUllqRJAkiI/pMd vsEoQwAWUB6cRmITHmW0BKEohAMHo1zyQq/e1YXwtFSFi93o1cjJNQlUfFXUISfXzcsV NCEQ== X-Gm-Message-State: AO0yUKXmiWP8CzFlXqmf8JwOZXB3zxe/YHr8WYCcEcGX5IE6qNGSanli ZCiDszBn5Zfl+v5ilNmTsk9fc5/Jyr/r/3BJLWP7hw== X-Google-Smtp-Source: AK7set/XeRnf1Y3LItkBjYGVD/6wc2VluTXjkvv30lvJGpBBnN5cjgbmbUaxHEgDAFOB11JlPk/oOyNtao1IV/YNKWs= X-Received: by 2002:a63:745a:0:b0:4fb:3c74:4d07 with SMTP id e26-20020a63745a000000b004fb3c744d07mr2766096pgn.7.1677238060167; Fri, 24 Feb 2023 03:27:40 -0800 (PST) MIME-Version: 1.0 References: <20230224055127.2500953-1-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Fri, 24 Feb 2023 12:27:26 +0100 Message-ID: Subject: Re: [PATCH v3 00/11] RISC-V: Add XThead* extension support To: Kito Cheng Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-3.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Feb 24, 2023 at 9:09 AM Kito Cheng wrote: > > Hi Christoph: > > OK for trunk for the 1~8, feel free to commit 1~8 after you address > those minor comments, and could you also prepare release notes for > those extensions? I addressed the comment regarding XTheadBs. But I have not done anything regarding XTheadB* and Zb*. Release notes patch can be found here: https://gcc.gnu.org/pipermail/gcc-patches/2023-February/612763.html > And 9~11 needs to take a few more rounds of review and test. I've seen the comments regarding patch 10 and 11. We will try to clean this up asap. In the patch for XTheadMemPair there was this nasty typo in one of the test= s, is there anything else that is needed? I believe that patch should be in a better shape than the last two patches and it is much less invasive. Further similar code can be found in other backends. Thanks, Christoph > > > > > On Fri, Feb 24, 2023 at 1:52 PM Christoph Muellner > wrote: > > > > From: Christoph M=C3=BCllner > > > > This series introduces support for the T-Head specific RISC-V ISA exten= sions > > which are available e.g. on the T-Head XuanTie C906. > > > > The ISA spec can be found here: > > https://github.com/T-head-Semi/thead-extension-spec > > > > This series adds support for the following XThead* extensions: > > * XTheadBa > > * XTheadBb > > * XTheadBs > > * XTheadCmo > > * XTheadCondMov > > * XTheadFMemIdx > > * XTheadFmv > > * XTheadInt > > * XTheadMac > > * XTheadMemIdx > > * XTheadMemPair > > * XTheadSync > > > > All extensions are properly integrated and the included tests > > demonstrate the improvements of the generated code. > > > > The series also introduces support for "-mcpu=3Dthead-c906", which also > > enables all available XThead* ISA extensions of the T-Head C906. > > > > All patches have been tested and don't introduce regressions for RV32 o= r RV64. > > The patches have also been tested with SPEC CPU2017 on QEMU and real HW > > (D1 board). > > > > Support patches for these extensions for Binutils, QEMU, and LLVM have > > already been merged in the corresponding upstream projects. > > > > Changes in v3: > > - Bugfix in XTheadBa > > - Rewrite of XTheadMemPair > > - Inclusion of XTheadMemIdx and XTheadFMemIdx > > > > Christoph M=C3=BCllner (9): > > riscv: Add basic XThead* vendor extension support > > riscv: riscv-cores.def: Add T-Head XuanTie C906 > > riscv: thead: Add support for the XTheadBa ISA extension > > riscv: thead: Add support for the XTheadBs ISA extension > > riscv: thead: Add support for the XTheadBb ISA extension > > riscv: thead: Add support for the XTheadCondMov ISA extensions > > riscv: thead: Add support for the XTheadMac ISA extension > > riscv: thead: Add support for the XTheadFmv ISA extension > > riscv: thead: Add support for the XTheadMemPair ISA extension > > > > moiz.hussain (2): > > riscv: thead: Add support for the XTheadMemIdx ISA extension > > riscv: thead: Add support for the XTheadFMemIdx ISA extension > > > > gcc/common/config/riscv/riscv-common.cc | 26 + > > gcc/config/riscv/bitmanip.md | 52 +- > > gcc/config/riscv/constraints.md | 43 + > > gcc/config/riscv/iterators.md | 4 + > > gcc/config/riscv/peephole.md | 56 + > > gcc/config/riscv/riscv-cores.def | 4 + > > gcc/config/riscv/riscv-opts.h | 29 + > > gcc/config/riscv/riscv-protos.h | 28 +- > > gcc/config/riscv/riscv.cc | 1090 +++++++++++++++-- > > gcc/config/riscv/riscv.h | 8 +- > > gcc/config/riscv/riscv.md | 169 ++- > > gcc/config/riscv/riscv.opt | 3 + > > gcc/config/riscv/thead.md | 351 ++++++ > > .../gcc.target/riscv/mcpu-thead-c906.c | 28 + > > .../gcc.target/riscv/xtheadba-addsl.c | 55 + > > gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 + > > .../gcc.target/riscv/xtheadbb-extu-2.c | 22 + > > .../gcc.target/riscv/xtheadbb-extu.c | 22 + > > gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 + > > gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 + > > .../gcc.target/riscv/xtheadbb-srri.c | 21 + > > gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 + > > gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 + > > .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 + > > .../riscv/xtheadcondmov-mveqz-imm-not.c | 38 + > > .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 + > > .../riscv/xtheadcondmov-mveqz-reg-not.c | 38 + > > .../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 + > > .../riscv/xtheadcondmov-mvnez-imm-nez.c | 38 + > > .../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 + > > .../riscv/xtheadcondmov-mvnez-reg-nez.c | 38 + > > .../gcc.target/riscv/xtheadcondmov.c | 14 + > > .../riscv/xtheadfmemidx-fldr-fstr.c | 58 + > > .../gcc.target/riscv/xtheadfmemidx.c | 14 + > > .../gcc.target/riscv/xtheadfmv-fmv.c | 24 + > > gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + > > gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + > > .../gcc.target/riscv/xtheadmac-mula-muls.c | 43 + > > gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 + > > .../gcc.target/riscv/xtheadmemidx-ldi-sdi.c | 72 ++ > > .../riscv/xtheadmemidx-ldr-str-32.c | 23 + > > .../riscv/xtheadmemidx-ldr-str-64.c | 53 + > > .../gcc.target/riscv/xtheadmemidx-macros.h | 110 ++ > > gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 + > > .../gcc.target/riscv/xtheadmempair-1.c | 98 ++ > > .../gcc.target/riscv/xtheadmempair-2.c | 84 ++ > > .../gcc.target/riscv/xtheadmempair-3.c | 29 + > > .../gcc.target/riscv/xtheadmempair.c | 13 + > > gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 + > > 52 files changed, 3048 insertions(+), 124 deletions(-) > > create mode 100644 gcc/config/riscv/thead.md > > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-= imm-eqz.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-= imm-not.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-= reg-eqz.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-= reg-not.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-= imm-cond.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-= imm-nez.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-= reg-cond.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-= reg-nez.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx-fldr-f= str.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.= c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldi-sdi= .c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldr-str= -32.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-ldr-str= -64.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx-macros.= h > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c > > create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c > > > > -- > > 2.39.2 > >