From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf31.google.com (mail-qv1-xf31.google.com [IPv6:2607:f8b0:4864:20::f31]) by sourceware.org (Postfix) with ESMTPS id 5FCEE38582B4 for ; Wed, 15 Jun 2022 08:56:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5FCEE38582B4 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-qv1-xf31.google.com with SMTP id 89so8418827qvc.0 for ; Wed, 15 Jun 2022 01:56:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=iMpr+KAMALnWuZMd26q9cRSzC9jGwlMDLCTqreR0GOs=; b=Jw9KgqC9XD7dwX8u6z/VRsdCfmKrFwfzYBP3WAsAVmk+T12veWU8UcizZaP3xp3UW4 CtRRjaJ30qW5O3l20j1BHf3SGlTuVsTgLM22ruMDjqIh1pQUZk0ru6cTr3GGnJ9Hi6Mr apezxBcGOEsB9dVzlJCDrg3CowIDhaD0KL1bm3DA3r2JlBfC0thQ7r9rvjJPOwBcajny 0/DMApPrp0Wlg5XVrb88vE42bd8serl0r2IQiTlKAAaxeNa55PbH1k6QKCHSEOpShkii 6OikvYfJLEqWq2fF/Z/kUXx4HAMCNW+vCXQnqxXwg7aCDiQSGFqxFnaaVMSjJzThwCL6 sqNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=iMpr+KAMALnWuZMd26q9cRSzC9jGwlMDLCTqreR0GOs=; b=f4dVfOmCxLQs/umTHIM6utnNx+qCxenugLDlSIuh0Po2jxl85epy8jAO3PCvGHbGLW 7Y0WdBUr8rc8gBfOZodY7LA7fWJEmS6DtNqKzSHL6//1LkmiVyBnh+Uyk0JUJR3t6/N7 LjCcHgqqy/Dv9O4IcYYieJW31Ay4zjo7kIKyPOpGDs5GX1a/6y8fQxQ0AhmJ9M5qeRpf 7af3PGXmFidYXKSZLO0Ma4lT6CRIVWvIm1UWkjnTTwDSzsbcRxKC3JEuB0/4oOr2C4al eLs4F/Dn6H4BypaV7dOm/GCyWJBI5QyFb1TiHultEIT5SOryXOR0xr/e/AyPpv4GZBss E2Xw== X-Gm-Message-State: AJIora/gbQtNe7FTuVNLPqsc3sZdWyspnTBFJwWWAdEBkFFiWHTaI5TK sOu0YodiEKmCe7BwLczMpRZpdJJXD0IkPP9OnsF18Q== X-Google-Smtp-Source: AGRyM1uCuQsjZ4QALg5VW96qOxrn8aPZHa9zYuSDwEVNE3ZQKVW8JGeGQbCjj+C0X0W8QvPx6zva2rpXG1VfOqvqjQM= X-Received: by 2002:a05:6214:242e:b0:464:5c29:ac8f with SMTP id gy14-20020a056214242e00b004645c29ac8fmr6952880qvb.121.1655283360756; Wed, 15 Jun 2022 01:56:00 -0700 (PDT) MIME-Version: 1.0 References: <20220613132042.2972081-1-christoph.muellner@vrull.eu> <20220613132042.2972081-2-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Wed, 15 Jun 2022 10:55:47 +0200 Message-ID: Subject: Re: [PATCH 2/2] riscv-cores.def: Add Allwinner D1 core To: Philipp Tomsich Cc: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Jun 2022 08:56:05 -0000 On Wed, Jun 15, 2022 at 10:39 AM Philipp Tomsich wrote: > > On Wed, 15 Jun 2022 at 10:30, Christoph M=C3=BCllner > wrote: > > > > On Mon, Jun 13, 2022 at 3:20 PM Christoph Muellner > > wrote: > > > > > > From: Christoph M=C3=BCllner > > > > > > This adds Allwinner's D1 to the list of known cores. > > > The Allwinner includes a single-core XuanTie C906 and is available > > > for quite some time. Note, that the tuning struct for the C906 > > > is already part of GCC. > > > > > > gcc/ChangeLog: > > > > > > * config/riscv/riscv-cores.def (RISCV_CORE): Add "allwinner-d= 1". > > > > > > Signed-off-by: Christoph M=C3=BCllner > > > --- > > > gcc/config/riscv/riscv-cores.def | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/risc= v-cores.def > > > index 60bcadbb034..dd97ece376f 100644 > > > --- a/gcc/config/riscv/riscv-cores.def > > > +++ b/gcc/config/riscv/riscv-cores.def > > > @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive= -7-series") > > > RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") > > > RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") > > > > > > +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") > > > > > > I just realized that this lacks a test case (other -mcpu=3D... entries = have one). > > And the core string is wrong (s/thead-c906/allwinner-d1). > > I will send a v2. > > Is the D1 different from the C906? I thought the D1 was using the C906 co= re? Yes, that's the case. I'll stick with "thead-c906" as core name for the v2. Thanks!