From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by sourceware.org (Postfix) with ESMTPS id 97B593858416 for ; Wed, 29 Nov 2023 15:03:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 97B593858416 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 97B593858416 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::1035 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701270221; cv=none; b=nE4bEHCpRDL5AzU6UnYg6Ba6p2/PEAYYtKy/irGskvpnkTqVcV7aTWOcDaeag0dU2i/9b9FysXHb+GDRT8dPRVvdfec+8T10jkr2EHbWst3tfFw/K3TY+Y+RqLyxkSNY1WV/9zCepqGsb2DBxf/TVA69RT9pyrzZFPYRE6tL5vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1701270221; c=relaxed/simple; bh=krcG3b7fvD30Urf0/CV7UdCZKdQ2QP5yPrPLSkFmL48=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=hUCvyp1D30+o2lZsdWV9mstML7TVMBgptnq6kGzUMbYLhM+a4ayUWJJEP+WaPK1U3uMqorLOCYOtxrhXY/QGOZ3SgKGg/9MoqqSXMrhtQxngPe0MYNpjHEMCzHg77oe3R/qpWLf4Ol86VPzCYO1x6pSEoVJ+91SrKg9HusxTKTU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-285a64dcf3eso3282295a91.1 for ; Wed, 29 Nov 2023 07:03:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1701270217; x=1701875017; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=SD1O+/v07oEoGAl4tk8wQLps15b1ip8a62rMKCjLBLg=; b=NI2ZX+YsK9HN97O4lvHXB4jMAHktBncOz+C6RF2hutydBTcYuaiUhWEQ/GtkhfknFe Jg85sZepYw3gS9haiQ4mHOqnGdjIBT366y18bAVFa4cHEmsHjzitBDUcFWe0lMgIynaP 4jYhGKVYrTFN9WvkQR9cb0IdJLJJDSfEGPuNM5n8ANDI4/K2/uc6OoV8Io/b5ANMzZNV GOUx2YEBMQxCT2iwY6e4HHidJnnsxknLU/CYG/NTU9ezcshbpesZ+KUnSC5VZWZVK05n SDAKV0q4axP/5AF7xbdTmnAsOsrjjF7Mdf6CYB2wbEPhR3/ClbZzzfX9ZxoA4ndtjXhe YUWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701270217; x=1701875017; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SD1O+/v07oEoGAl4tk8wQLps15b1ip8a62rMKCjLBLg=; b=hhe3kXgHkBz0MOvjUHRWtdOs/VJ5ofGR2NZGA62R5vbZSS103SPoqjeZ38lPkB+gyP 9FvVk4fCrsRsTWuq+MYdEUott5QHFEWdJLOixenshSYA4QJFSw1KwJme3u8ZH09LtFBQ d17w659FVdy+hagC/gqJe9A1h21sInpCJqDMwLkAo5lNcrwFcp8ZtD5sNgwL6A8efnkR cuZxj1U9N8XSyPEPv8R/ugkFUEfFGuLLEMTRE4wm5C7tbcFDBEBBfga7RiKivjYsI1kz 684oQCFx0jZfHR3O1TDsxUk3EbOB0CCjOr5duBQ1T8kueeOqsfUI1Fzy77unnJO/mTuT JiXg== X-Gm-Message-State: AOJu0YyHdaep86XLnbQPi8ga8cSXokA6IcdCdlJse2U/P02mrOvcjy0F jsiYYP7lyQk3AdU2oBlZ0tWpKMe0+rPndvXTLTtuKw== X-Google-Smtp-Source: AGHT+IG4O7xxPhzJGo3yr8OxKsryaXQ+hCebfK9wcVv+ZaLw3Ol3GBVDuiqhGVcn/UNDHDM8uKXunPYe8OZWThXEfWM= X-Received: by 2002:a17:90b:1e46:b0:285:afac:49f2 with SMTP id pi6-20020a17090b1e4600b00285afac49f2mr12036836pjb.15.1701270217222; Wed, 29 Nov 2023 07:03:37 -0800 (PST) MIME-Version: 1.0 References: <20231127083458.307226-1-shihua@iscas.ac.cn> In-Reply-To: <20231127083458.307226-1-shihua@iscas.ac.cn> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Wed, 29 Nov 2023 16:03:25 +0100 Message-ID: Subject: Re: [PATCH] Add C intrinsics for scalar crypto extension To: Liao Shihua Cc: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, shiyulong@iscas.ac.cn, jiawei@iscas.ac.cn, chenyixuan@iscas.an.cn, craig.topper@sifive.com, palmer@rivosinc.com, jeffreyalaw@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Nov 27, 2023 at 9:36=E2=80=AFAM Liao Shihua wr= ote: > > This patch add C intrinsics for scalar crypto extension. > Because of riscv-c-api (https://github.com/riscv-non-isa/riscv-c-api-doc/= pull/44/files) includes zbkb/zbkc/zbkx's > intrinsics in bit manipulation extension, this patch only support zkn*/zk= s*'s intrinsics. Thanks for working on this! Looking forward to seeing the second patch (covering bitmanip) soon as well= ! A couple of comments can be found below. > > gcc/ChangeLog: > > * config.gcc: Add riscv_crypto.h > * config/riscv/riscv_crypto.h: New file. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zknd32.c: Use intrinsics instead of builtins. > * gcc.target/riscv/zknd64.c: Likewise. > * gcc.target/riscv/zkne32.c: Likewise. > * gcc.target/riscv/zkne64.c: Likewise. > * gcc.target/riscv/zknh-sha256-32.c: Likewise. > * gcc.target/riscv/zknh-sha256-64.c: Likewise. > * gcc.target/riscv/zknh-sha512-32.c: Likewise. > * gcc.target/riscv/zknh-sha512-64.c: Likewise. > * gcc.target/riscv/zksed32.c: Likewise. > * gcc.target/riscv/zksed64.c: Likewise. > * gcc.target/riscv/zksh32.c: Likewise. > * gcc.target/riscv/zksh64.c: Likewise. > > --- > gcc/config.gcc | 2 +- > gcc/config/riscv/riscv_crypto.h | 219 ++++++++++++++++++ > gcc/testsuite/gcc.target/riscv/zknd32.c | 6 +- > gcc/testsuite/gcc.target/riscv/zknd64.c | 12 +- > gcc/testsuite/gcc.target/riscv/zkne32.c | 6 +- > gcc/testsuite/gcc.target/riscv/zkne64.c | 10 +- > .../gcc.target/riscv/zknh-sha256-32.c | 22 +- > .../gcc.target/riscv/zknh-sha256-64.c | 10 +- > .../gcc.target/riscv/zknh-sha512-32.c | 14 +- > .../gcc.target/riscv/zknh-sha512-64.c | 10 +- > gcc/testsuite/gcc.target/riscv/zksed32.c | 6 +- > gcc/testsuite/gcc.target/riscv/zksed64.c | 6 +- > gcc/testsuite/gcc.target/riscv/zksh32.c | 6 +- > gcc/testsuite/gcc.target/riscv/zksh64.c | 6 +- > 14 files changed, 288 insertions(+), 47 deletions(-) > create mode 100644 gcc/config/riscv/riscv_crypto.h > > diff --git a/gcc/config.gcc b/gcc/config.gcc > index b88591b6fd8..d67fe8b6a6f 100644 > --- a/gcc/config.gcc > +++ b/gcc/config.gcc > @@ -548,7 +548,7 @@ riscv*) > extra_objs=3D"${extra_objs} riscv-vector-builtins.o riscv-vector-= builtins-shapes.o riscv-vector-builtins-bases.o" > extra_objs=3D"${extra_objs} thead.o riscv-target-attr.o" > d_target_objs=3D"riscv-d.o" > - extra_headers=3D"riscv_vector.h" > + extra_headers=3D"riscv_vector.h riscv_crypto.h" > target_gtfiles=3D"$target_gtfiles \$(srcdir)/config/riscv/riscv-v= ector-builtins.cc" > target_gtfiles=3D"$target_gtfiles \$(srcdir)/config/riscv/riscv-v= ector-builtins.h" > ;; > diff --git a/gcc/config/riscv/riscv_crypto.h b/gcc/config/riscv/riscv_cry= pto.h > new file mode 100644 > index 00000000000..149c1132e10 > --- /dev/null > +++ b/gcc/config/riscv/riscv_crypto.h > @@ -0,0 +1,219 @@ > +/* RISC-V 'K' Extension intrinsics include file. > + Copyright (C) 2023 Free Software Foundation, Inc. > + > + This file is part of GCC. > + > + GCC is free software; you can redistribute it and/or modify it > + under the terms of the GNU General Public License as published > + by the Free Software Foundation; either version 3, or (at your > + option) any later version. > + > + GCC is distributed in the hope that it will be useful, but WITHOUT > + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY > + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > + License for more details. > + > + Under Section 7 of GPL version 3, you are granted additional > + permissions described in the GCC Runtime Library Exception, version > + 3.1, as published by the Free Software Foundation. > + > + You should have received a copy of the GNU General Public License and > + a copy of the GCC Runtime Library Exception along with this program; > + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > + . */ > + > +#ifndef __RISCV_CRYPTO_H > +#define __RISCV_CRYPTO_H > + > +#include > + > +#if defined (__cplusplus) > +extern "C" { > +#endif > + > +#if defined(__riscv_zknd) > +#if __riscv_xlen =3D=3D 32 > +#define __riscv_aes32dsi(x, y, bs) __builtin_riscv_aes32dsi(x, y, bs) > +#define __riscv_aes32dsmi(x, y, bs) __builtin_riscv_aes32dsmi(x, y, bs) > +#endif > + > +#if __riscv_xlen =3D=3D 64 > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_aes64ds (uint64_t __x, uint64_t __y) > +{ > + return __builtin_riscv_aes64ds (__x, __y); > +} I don't understand why some intrinsic functions are implemented as macros to builtins and some are implemented as static inline wrappers around butilins. Is there a particular reason that this is mixed? > + > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_aes64dsm (uint64_t __x, uint64_t __y) > +{ > + return __builtin_riscv_aes64dsm (__x, __y); > +} > + > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_aes64im (uint64_t __x) > +{ > + return __builtin_riscv_aes64im (__x); > +} > +#endif > +#endif // defined (__riscv_zknd) > + > +#if defined(__riscv_zkne) > +#if __riscv_xlen =3D=3D 32 > +#define __riscv_aes32esi(x, y, bs) __builtin_riscv_aes32esi(x, y, bs) > +#define __riscv_aes32esmi(x, y, bs) __builtin_riscv_aes32esmi(x, y, bs) > +#endif > + > +#if __riscv_xlen =3D=3D 64 > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_aes64es (uint64_t __x, uint64_t __y) > +{ > + return __builtin_riscv_aes64es (__x, __y); > +} > + > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_aes64esm (uint64_t __x, uint64_t __y) > +{ > + return __builtin_riscv_aes64esm (__x, __y); > +} > +#endif > +#endif // defined (__riscv_zknd) Copy and paste mistake in the comment (should be "__riscv_zkne") > + > +#if defined(__riscv_zknd) || defined(__riscv_zkne) > +#if __riscv_xlen =3D=3D 64 > +#define __riscv_aes64ks1i(x, rnum) __builtin_riscv_aes64ks1i(x, rnum) > + > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_aes64ks2 (uint64_t __x, uint64_t __y) > +{ > + return __builtin_riscv_aes64ks2 (__x, __y); > +} > +#endif > +#endif // defined (__riscv_zknd) || defined (__riscv_zkne) > + > +#if defined(__riscv_zknh) > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha256sig0 (uint32_t __x) > +{ > + return __builtin_riscv_sha256sig0 (__x); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha256sig1 (uint32_t __x) > +{ > + return __builtin_riscv_sha256sig1 (__x); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha256sum0 (uint32_t __x) > +{ > + return __builtin_riscv_sha256sum0 (__x); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha256sum1 (uint32_t __x) > +{ > + return __builtin_riscv_sha256sum1 (__x); > +} > + > +#if __riscv_xlen =3D=3D 32 > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sig0h (uint32_t __x, uint32_t __y) > +{ > + return __builtin_riscv_sha512sig0h (__x, __y); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sig0l (uint32_t __x, uint32_t __y) > +{ > + return __builtin_riscv_sha512sig0l (__x, __y); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sig1h (uint32_t __x, uint32_t __y) > +{ > + return __builtin_riscv_sha512sig1h (__x, __y); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sig1l (uint32_t __x, uint32_t __y) > +{ > + return __builtin_riscv_sha512sig1l (__x, __y); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sum0l (uint32_t __x, uint32_t __y) > +{ > + return __builtin_riscv_sha512sum0l (__x, __y); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sum0r (uint32_t __x, uint32_t __y) > +{ > + return __builtin_riscv_sha512sum0r (__x, __y); > +} Why sum0l and sum0r? The specification says sum0h and sum0l. > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sum1l (uint32_t __x, uint32_t __y) > +{ > + return __builtin_riscv_sha512sum1l (__x, __y); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sum1r (uint32_t __x, uint32_t __y) > +{ > + return __builtin_riscv_sha512sum1r (__x, __y); > +} Why sum1l and sum1r? The specification says sum1h and sum1l. > +#endif > + > +#if __riscv_xlen =3D=3D 64 > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sig0 (uint64_t __x) > +{ > + return __builtin_riscv_sha512sig0 (__x); > +} > + > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sig1 (uint64_t __x) > +{ > + return __builtin_riscv_sha512sig1 (__x); > +} > + > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sum0 (uint64_t __x) > +{ > + return __builtin_riscv_sha512sum0 (__x); > +} > + > +static __inline__ uint64_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sha512sum1 (uint64_t __x) > +{ > + return __builtin_riscv_sha512sum1 (__x); > +} > +#endif > +#endif // defined (__riscv_zknh) > + > +#if defined(__riscv_zksh) > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sm3p0 (uint32_t __x) > +{ > + return __builtin_riscv_sm3p0 (__x); > +} > + > +static __inline__ uint32_t __attribute__ ((__always_inline__, __nodebug_= _)) > +__riscv_sm3p1 (uint32_t __x) > +{ > + return __builtin_riscv_sm3p1 (__x); > +} > +#endif // defined (__riscv_zksh) > + > +#if defined(__riscv_zksed) > +#define __riscv_sm4ed(x, y, bs) __builtin_riscv_sm4ed(x, y, bs); > +#define __riscv_sm4ks(x, y, bs) __builtin_riscv_sm4ks(x, y, bs); > +#endif // defined (__riscv_zksh) Wrong comment (should be "__riscv_zksed"). > + > +#if defined(__cplusplus) > +} > +#endif > + > +#endif > \ No newline at end of file > diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c b/gcc/testsuite/gcc.= target/riscv/zknd32.c > index e60c027e091..62b730a700f 100644 > --- a/gcc/testsuite/gcc.target/riscv/zknd32.c > +++ b/gcc/testsuite/gcc.target/riscv/zknd32.c > @@ -2,16 +2,16 @@ > /* { dg-options "-O2 -march=3Drv32gc_zknd -mabi=3Dilp32d" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint32_t foo1(uint32_t rs1, uint32_t rs2, int bs) > { > - return __builtin_riscv_aes32dsi(rs1,rs2,bs); > + return __riscv_aes32dsi(rs1,rs2,bs); > } > > uint32_t foo2(uint32_t rs1, uint32_t rs2, int bs) > { > - return __builtin_riscv_aes32dsmi(rs1,rs2,bs); > + return __riscv_aes32dsmi(rs1,rs2,bs); > } > > /* { dg-final { scan-assembler-times "aes32dsi" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.= target/riscv/zknd64.c > index 707418cd51e..e5f2be72bae 100644 > --- a/gcc/testsuite/gcc.target/riscv/zknd64.c > +++ b/gcc/testsuite/gcc.target/riscv/zknd64.c > @@ -2,31 +2,31 @@ > /* { dg-options "-O2 -march=3Drv64gc_zknd -mabi=3Dlp64" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint64_t foo1(uint64_t rs1, uint64_t rs2) > { > - return __builtin_riscv_aes64ds(rs1,rs2); > + return __riscv_aes64ds(rs1,rs2); > } > > uint64_t foo2(uint64_t rs1, uint64_t rs2) > { > - return __builtin_riscv_aes64dsm(rs1,rs2); > + return __riscv_aes64dsm(rs1,rs2); > } > > uint64_t foo3(uint64_t rs1, unsigned rnum) > { > - return __builtin_riscv_aes64ks1i(rs1,rnum); > + return __riscv_aes64ks1i(rs1,rnum); > } > > uint64_t foo4(uint64_t rs1, uint64_t rs2) > { > - return __builtin_riscv_aes64ks2(rs1,rs2); > + return __riscv_aes64ks2(rs1,rs2); > } > > uint64_t foo5(uint64_t rs1) > { > - return __builtin_riscv_aes64im(rs1); > + return __riscv_aes64im(rs1); > } > > /* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zkne32.c b/gcc/testsuite/gcc.= target/riscv/zkne32.c > index 252e9ffa43b..c3a7205a48b 100644 > --- a/gcc/testsuite/gcc.target/riscv/zkne32.c > +++ b/gcc/testsuite/gcc.target/riscv/zkne32.c > @@ -2,16 +2,16 @@ > /* { dg-options "-O2 -march=3Drv32gc_zkne -mabi=3Dilp32d" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint32_t foo1(uint32_t rs1, uint32_t rs2, unsigned bs) > { > - return __builtin_riscv_aes32esi(rs1, rs2, bs); > + return __riscv_aes32esi(rs1, rs2, bs); > } > > uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) > { > - return __builtin_riscv_aes32esmi(rs1, rs2, bs); > + return __riscv_aes32esmi(rs1, rs2, bs); > } > > /* { dg-final { scan-assembler-times "aes32esi" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zkne64.c b/gcc/testsuite/gcc.= target/riscv/zkne64.c > index b25f6b5c29a..e99b21a46dd 100644 > --- a/gcc/testsuite/gcc.target/riscv/zkne64.c > +++ b/gcc/testsuite/gcc.target/riscv/zkne64.c > @@ -2,26 +2,26 @@ > /* { dg-options "-O2 -march=3Drv64gc_zkne -mabi=3Dlp64" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint64_t foo1(uint64_t rs1, uint64_t rs2) > { > - return __builtin_riscv_aes64es(rs1,rs2); > + return __riscv_aes64es(rs1,rs2); > } > > uint64_t foo2(uint64_t rs1, uint64_t rs2) > { > - return __builtin_riscv_aes64esm(rs1,rs2); > + return __riscv_aes64esm(rs1,rs2); > } > > uint64_t foo3(uint64_t rs1, unsigned rnum) > { > - return __builtin_riscv_aes64ks1i(rs1,rnum); > + return __riscv_aes64ks1i(rs1,rnum); > } > > uint64_t foo4(uint64_t rs1, uint64_t rs2) > { > - return __builtin_riscv_aes64ks2(rs1,rs2); > + return __riscv_aes64ks2(rs1,rs2); > } > > /* { dg-final { scan-assembler-times "aes64es\t" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c b/gcc/testsu= ite/gcc.target/riscv/zknh-sha256-32.c > index c51b143a8a5..96e967fba96 100644 > --- a/gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c > +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c > @@ -2,7 +2,27 @@ > /* { dg-options "-O2 -march=3Drv32gc_zknh -mabi=3Dilp32d" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include "zknh-sha256-64.c" > +#include "riscv_crypto.h" > + > +unsigned int foo1(unsigned int rs1) > +{ > + return __riscv_sha256sig0(rs1); > +} > + > +unsigned int foo2(unsigned int rs1) > +{ > + return __riscv_sha256sig1(rs1); > +} > + > +unsigned int foo3(unsigned int rs1) > +{ > + return __riscv_sha256sum0(rs1); > +} > + > +unsigned int foo4(unsigned int rs1) > +{ > + return __riscv_sha256sum1(rs1); > +} > > /* { dg-final { scan-assembler-times "sha256sig0" 1 } } */ > /* { dg-final { scan-assembler-times "sha256sig1" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c b/gcc/testsu= ite/gcc.target/riscv/zknh-sha256-64.c > index 2ef37601e6f..172b84421e2 100644 > --- a/gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c > +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256-64.c > @@ -2,24 +2,26 @@ > /* { dg-options "-O2 -march=3Drv64gc_zknh -mabi=3Dlp64" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > +#include "riscv_crypto.h" > + > unsigned int foo1(unsigned int rs1) > { > - return __builtin_riscv_sha256sig0(rs1); > + return __riscv_sha256sig0(rs1); > } > > unsigned int foo2(unsigned int rs1) > { > - return __builtin_riscv_sha256sig1(rs1); > + return __riscv_sha256sig1(rs1); > } > > unsigned int foo3(unsigned int rs1) > { > - return __builtin_riscv_sha256sum0(rs1); > + return __riscv_sha256sum0(rs1); > } > > unsigned int foo4(unsigned int rs1) > { > - return __builtin_riscv_sha256sum1(rs1); > + return __riscv_sha256sum1(rs1); > } > > /* { dg-final { scan-assembler-times "sha256sig0" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c b/gcc/testsu= ite/gcc.target/riscv/zknh-sha512-32.c > index f2bcae36a1f..e6fb298d6a7 100644 > --- a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c > +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c > @@ -2,36 +2,36 @@ > /* { dg-options "-O2 -march=3Drv32gc_zknh -mabi=3Dilp32" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint32_t foo1(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sha512sig0h(rs1,rs2); > + return __riscv_sha512sig0h(rs1,rs2); > } > > uint32_t foo2(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sha512sig0l(rs1,rs2); > + return __riscv_sha512sig0l(rs1,rs2); > } > > uint32_t foo3(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sha512sig1h(rs1,rs2); > + return __riscv_sha512sig1h(rs1,rs2); > } > > uint32_t foo4(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sha512sig1l(rs1,rs2); > + return __riscv_sha512sig1l(rs1,rs2); > } > > uint32_t foo5(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sha512sum0r(rs1,rs2); > + return __riscv_sha512sum0r(rs1,rs2); > } > > uint32_t foo6(uint32_t rs1, uint32_t rs2) > { > - return __builtin_riscv_sha512sum1r(rs1,rs2); > + return __riscv_sha512sum1r(rs1,rs2); > } > > /* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c b/gcc/testsu= ite/gcc.target/riscv/zknh-sha512-64.c > index 4f248575e66..c65c2043d08 100644 > --- a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c > +++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c > @@ -2,26 +2,26 @@ > /* { dg-options "-O2 -march=3Drv64gc_zknh -mabi=3Dlp64" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint64_t foo1(uint64_t rs1) > { > - return __builtin_riscv_sha512sig0(rs1); > + return __riscv_sha512sig0(rs1); > } > > uint64_t foo2(uint64_t rs1) > { > - return __builtin_riscv_sha512sig1(rs1); > + return __riscv_sha512sig1(rs1); > } > > uint64_t foo3(uint64_t rs1) > { > - return __builtin_riscv_sha512sum0(rs1); > + return __riscv_sha512sum0(rs1); > } > > uint64_t foo4(uint64_t rs1) > { > - return __builtin_riscv_sha512sum1(rs1); > + return __riscv_sha512sum1(rs1); > } > > > diff --git a/gcc/testsuite/gcc.target/riscv/zksed32.c b/gcc/testsuite/gcc= .target/riscv/zksed32.c > index 0e8f01cd548..d63e0775391 100644 > --- a/gcc/testsuite/gcc.target/riscv/zksed32.c > +++ b/gcc/testsuite/gcc.target/riscv/zksed32.c > @@ -2,16 +2,16 @@ > /* { dg-options "-O2 -march=3Drv32gc_zksed -mabi=3Dilp32" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint32_t foo1(uint32_t rs1, uint32_t rs2, unsigned bs) > { > - return __builtin_riscv_sm4ks(rs1,rs2,bs); > + return __riscv_sm4ks(rs1,rs2,bs); > } > > uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) > { > - return __builtin_riscv_sm4ed(rs1,rs2,bs); > + return __riscv_sm4ed(rs1,rs2,bs); > } > > > diff --git a/gcc/testsuite/gcc.target/riscv/zksed64.c b/gcc/testsuite/gcc= .target/riscv/zksed64.c > index 9e4d1961419..426122cf6eb 100644 > --- a/gcc/testsuite/gcc.target/riscv/zksed64.c > +++ b/gcc/testsuite/gcc.target/riscv/zksed64.c > @@ -2,16 +2,16 @@ > /* { dg-options "-O2 -march=3Drv64gc_zksed -mabi=3Dlp64" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint32_t foo1(uint32_t rs1, uint32_t rs2, unsigned bs) > { > - return __builtin_riscv_sm4ks(rs1,rs2,bs); > + return __riscv_sm4ks(rs1,rs2,bs); > } > > uint32_t foo2(uint32_t rs1, uint32_t rs2, unsigned bs) > { > - return __builtin_riscv_sm4ed(rs1,rs2,bs); > + return __riscv_sm4ed(rs1,rs2,bs); > } > > > diff --git a/gcc/testsuite/gcc.target/riscv/zksh32.c b/gcc/testsuite/gcc.= target/riscv/zksh32.c > index c182e557a85..3d0d154ad1d 100644 > --- a/gcc/testsuite/gcc.target/riscv/zksh32.c > +++ b/gcc/testsuite/gcc.target/riscv/zksh32.c > @@ -2,16 +2,16 @@ > /* { dg-options "-O2 -march=3Drv32gc_zksh -mabi=3Dilp32" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint32_t foo1(uint32_t rs1) > { > - return __builtin_riscv_sm3p0(rs1); > + return __riscv_sm3p0(rs1); > } > > uint32_t foo2(uint32_t rs1) > { > - return __builtin_riscv_sm3p1(rs1); > + return __riscv_sm3p1(rs1); > } > > > diff --git a/gcc/testsuite/gcc.target/riscv/zksh64.c b/gcc/testsuite/gcc.= target/riscv/zksh64.c > index d794b39f77a..1398c1329f0 100644 > --- a/gcc/testsuite/gcc.target/riscv/zksh64.c > +++ b/gcc/testsuite/gcc.target/riscv/zksh64.c > @@ -2,16 +2,16 @@ > /* { dg-options "-O2 -march=3Drv64gc_zksh -mabi=3Dlp64" } */ > /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */ > > -#include > +#include "riscv_crypto.h" > > uint32_t foo1(uint32_t rs1) > { > - return __builtin_riscv_sm3p0(rs1); > + return __riscv_sm3p0(rs1); > } > > uint32_t foo2(uint32_t rs1) > { > - return __builtin_riscv_sm3p1(rs1); > + return __riscv_sm3p1(rs1); > } > > > -- > 2.34.1 >