From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by sourceware.org (Postfix) with ESMTPS id E1A783858C41 for ; Thu, 9 Nov 2023 08:06:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E1A783858C41 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E1A783858C41 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::102b ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699517174; cv=none; b=ARW8vCLgh1A8bOP+ay3EQ7ePztXqAQs7coyCH3zC8VDsMrbd7QVtV0boeyehSD+gK5FKRB73sIUqkdsMW+sMp8m4+4+qDxsfkCiyzGTw7ePcu/ZkAidf/95rEAdblaASxlGxzL9AAADT34wLuDTJbAZOVJULyL73EglJPffKS/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699517174; c=relaxed/simple; bh=3TtcsNPTVXl+mTTVZiyp/veCX6JWeo0BLi5idER9DHk=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=gJpEfZ0QLS+DbxJvUZUh46HUspmwvsxKi8cIOYRjM1PMH6Pe6Wonn3MBvOu0VwF9hqHokqXzvRQKsLjukQRIdeFuAp8axoA9Z59Coajd93NBM+9nVOvzJSeGkDVzyfCWeAsvEtI3LdBAT1FPCdlNZPZMVAg7cgPToVL0svARcqk= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-2809414efa9so555910a91.1 for ; Thu, 09 Nov 2023 00:06:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1699517171; x=1700121971; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=KVWbIV+M+seyarvTZRTvH+Lt68VH9qP3QZu64R0O50Q=; b=cWd32xhAF+xF7CAgkw8FRUqRVaBIybmuK/xIQjjeJzL8P8j3BZzQV/VTwohBkSvGeY u+EL7Kr27Uxl/LtGxXzN3aVtN+NZ4HjdkxhDh+eK2IzF2hA3BFzrhQ+1gFCupBNZaNjC rf6WIQqW8ybmg63Ds40xFRg2tH8jMWY89jvb/2j7rQnRtc+favKGVTrHVFBNxOivFvXV t6hwOuDuCbxePboX+C3QiSbOq6auCZjSg1gFDhHTKyGvkD3wxqFqK8c0kwIkl+jS/bef iU548hX6hPg6HIRMTfqLORGQnrWr27gSElDSbyU+Hgw1OzvKv2sD9b6QzEihat4RvUw6 aI6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699517171; x=1700121971; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KVWbIV+M+seyarvTZRTvH+Lt68VH9qP3QZu64R0O50Q=; b=jZeiMV52hOHGfmLaCG3yiwDVIl4SWVOG9OPVxY4H3d7SqtnauqEVrEJC6Ea69icfcO Bs1R4f+qjxQMu6hGFvupIupJOMcyGygPkERk9W/EAxb72AVfkqmNtBY43eM+vuLR8vtu 6SEdL0b/RqSV9dFvJW9qVdbJglH3Q4WmcZ+RWTRaBAtOta9HhfDuvw7ngJ1VVAvt91Sq 3ep+taCPMp9ZA0gDnoi3V7Jd3lv5ezMp1epIVuY1Z6oEwJ8Alj9n8wOvU7cMg3vWruOv xy9xVaJ5SL4KjJtcYGcaqBmf5qBmxwITZi3UQGezD2ji9nbkQhfTguvQgtTMxvmzVX6Y l1dQ== X-Gm-Message-State: AOJu0Yy/COt1U3jUgXecUyaj0j606TVXVcBLlrzX5c7eP4pEoI6fh7gF KOS53nPXtYsbAuPdtHLfdpWtVVyzFJk6leLEgITzmw== X-Google-Smtp-Source: AGHT+IF/o5c/3SGxqdWbOPlCeSdePXm8fwUeB2dzpS2CnloqDambaQZV/rmiAq9SlKn8CkC/oIuFDesX5KxwzAL8umM= X-Received: by 2002:a17:90a:e54f:b0:27c:efe3:89dc with SMTP id ei15-20020a17090ae54f00b0027cefe389dcmr881706pjb.14.1699517170675; Thu, 09 Nov 2023 00:06:10 -0800 (PST) MIME-Version: 1.0 References: <20231108131237.3672914-1-chenyixuan@iscas.ac.cn> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Thu, 9 Nov 2023 09:05:54 +0100 Message-ID: Subject: Re: [PATCH] minimal support for xtheadv To: Kito Cheng Cc: chenyixuan@iscas.ac.cn, gcc-patches@gcc.gnu.org, shiyulong@iscas.ac.cn, oriachiuan@gmail.com, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, Jojo R , Philipp Tomsich , Cooper Qu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Thu, Nov 9, 2023 at 8:39=E2=80=AFAM Kito Cheng wr= ote: > > Hi Yi Xuan: > > This patch is trivial, and generally LGTM, but I would require putting > the spec into https://github.com/riscv-non-isa/riscv-toolchain-convention= s > before merging this, also don't forget include "RISC-V:" in the title, > it would be easier to track during the RISC-V GCC sync meeting :) > > And I am a little bit confused by the author's info? is it from you or > "XYenChi "? or oriachiuan@gmail.com is also your > mail address? > > cc Christoph since I believe you may know more about that process. > cc JoJo since you are T-head folk :P Hi Yi Xuan and Kito, I was not aware that CAS is working on getting T-Head's Vector extension supported. My biggest concern with this patch is that "XTheadV" does not have a specification. T-Head and VRULL are currently working on support patches for T-Head's Vector extension implementation. We've named the extension XTheadVector. Supporting XTheadVector means to address a range of issues (e.g. defining a formal ISA vendor extension specification, extension discovery, addressing implementation details, differences among available cores, intrinsics, ...). We've already made good progress on that and expect to publish first results soon. BR Christoph > > > On Wed, Nov 8, 2023 at 9:13=E2=80=AFPM wrote: > > > > From: XYenChi > > > > This patch is for support xtheadv. > > > > gcc/ChangeLog: > > > > 2023-11-08 Chen Yixuan > > > > * common/config/riscv/riscv-common.cc: Add xthead minimal suppo= rt. > > > > gcc/config/ChangeLog: > > > > 2023-11-08 Chen Yixuan > > > > * riscv/riscv.opt: Add xthead minimal support. > > --- > > gcc/common/config/riscv/riscv-common.cc | 2 ++ > > gcc/config/riscv/riscv.opt | 2 ++ > > 2 files changed, 4 insertions(+) > > > > diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/confi= g/riscv/riscv-common.cc > > index 526dbb7603b..d5ea0ee9b70 100644 > > --- a/gcc/common/config/riscv/riscv-common.cc > > +++ b/gcc/common/config/riscv/riscv-common.cc > > @@ -325,6 +325,7 @@ static const struct riscv_ext_version riscv_ext_ver= sion_table[] =3D > > {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, > > {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0}, > > {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, > > + {"xtheadv", ISA_SPEC_CLASS_NONE, 0, 7}, > > > > {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0}, > > > > @@ -1680,6 +1681,7 @@ static const riscv_ext_flag_table_t riscv_ext_fla= g_table[] =3D > > {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADME= MIDX}, > > {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADME= MPAIR}, > > {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSY= NC}, > > + {"xtheadv", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADV}= , > > > > {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVEN= TANACONDOPS}, > > > > diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt > > index 70d78151cee..2bbdf680fa2 100644 > > --- a/gcc/config/riscv/riscv.opt > > +++ b/gcc/config/riscv/riscv.opt > > @@ -438,6 +438,8 @@ Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext) > > > > Mask(XTHEADSYNC) Var(riscv_xthead_subext) > > > > +Mask(XTHEADV) Var(riscv_xthead_subext) > > + > > TargetVariable > > int riscv_xventana_subext > > > > -- > > 2.42.0 > >