From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id E64C33858C98 for ; Fri, 22 Mar 2024 08:00:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E64C33858C98 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E64C33858C98 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::102e ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1711094433; cv=none; b=Y7N1ULZiFLtDZXydKAUE+wfsHYd2cuXz+6lm9LSo0xQwB6EKhUYZTQeBZC+Rhv8yYEjqiHTy1ah2LIqP6+EGadGjMfD5S6YKaDtzXRTsMiIo+m6JxvlnoH8MLFg2/C5ytIhnU4td7C9/pFd2RWZctBOyxCVpis3UOKu4701Y0t8= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1711094433; c=relaxed/simple; bh=+I7w5TsM1db0KcOzxJSgWi8Jko1EDe9vZD4q/cNXT2I=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=pUZCjydmkF975yY9I6xGm8mT15sn9LEYq1bidS4LmgkicMYJqzifZqeVNBOV2QkHjeT3E4qDmnHfQuBK2C8jJpUknh1JWh9zcx9s75XQhII2k67Fxplhgof8BETBBMS+yBXTnPVwFFIkHyYkE2X8x2yUIkIqTdTRTATIueQWcL0= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-29e0a1fd9a7so1245176a91.2 for ; Fri, 22 Mar 2024 01:00:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1711094427; x=1711699227; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=k8YdS80Ghm0lPRnUuocsGFxtH4qm6rS+bkiuSdh5P/A=; b=OqtGNINxt3WvTlADycOVGo2a84Ci3eomnXhZFON4OrjqJ7T45C7wi7w263/Q+6i61X NGGNFhy4VbdfVhi1EKN1+dEfBSNoNxvrHQPSJJVc0hozP+ltt9Ktd0rQeNUo7wv8nFPw BktbVj/xN/NzUowTY+NrZG9gCGV3xFMdOM6QNXoB69MkvfXdLKn9WxV4vIrPLpJSR1f6 umeSqLdtM495hQ8tNJx6S5sdVs4ViM626acN4+246vWGYSw5VuwdmgZn9JEbE4Gdbgo0 9ehpZeIhisaejWquKMOLt/FBGFfC7U+Yv7CLb3ZoR9QI4vneIf1EtVWRe8rNATfwMbt+ LivQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711094427; x=1711699227; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k8YdS80Ghm0lPRnUuocsGFxtH4qm6rS+bkiuSdh5P/A=; b=cFwSvRED7918y2996+xW+QSRJ4z2wsrM23sXIX0yFr5kaqc9pHnw4fMRWlWWPh7qGq eLMP46yssiEfqXs9uQlj12CruLCo4oSjyn4JbDuzbEudSSQTPlxUvYt/ozIkZD/4s41S ZmVal0HD9W6oFeJ/5GpHIY3X8EHnymBhh5DkGU2uc7Ui0NjihIhYOBMx1FLlrq+8cVs8 +70BUgkW6BzV3HLKJVQ/pKoic992H5i7MJfLpWKNGKTTjOV08La2YYKHtGl7eIpRH5jD q6PMqFFW6bN/0VSfXocOj6fwnuqhiVAE5S58xjQqmUmD+eiNhyagr+Z7y8VGx4gQUPlS FwgA== X-Gm-Message-State: AOJu0YwspDeQ2Rkcmki9R5F+1u8FtFgzdpGnTg8xYRXe7bf9uhX48nGt SzHncQBnusB1qcrSK4UEN+MBsSaQ63Mk5Yin/vIQmkFgnoYL0GWAFY6aTiXTB5+IhRKIncqyTmD teAcghc6QS3ghR9UJAMLap7R9uP+38X8R5hTSmXrKEsdSjoTT0F4= X-Google-Smtp-Source: AGHT+IGEWvjhThr3yitN+b2khSxMUo/jYRI84eejdudGKFZk7vkvSJn1I/SDsXd0Sh5yUPjKRRx6+Kv1757imV4MJYY= X-Received: by 2002:a05:6a20:4392:b0:1a3:6b62:3981 with SMTP id i18-20020a056a20439200b001a36b623981mr2229902pzl.45.1711090511169; Thu, 21 Mar 2024 23:55:11 -0700 (PDT) MIME-Version: 1.0 References: <20240321234552.2140254-1-christoph.muellner@vrull.eu> <1019449B8F0CA853+202403220917589896590@rivai.ai> In-Reply-To: <1019449B8F0CA853+202403220917589896590@rivai.ai> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Fri, 22 Mar 2024 07:54:59 +0100 Message-ID: Subject: Re: [PATCH] RISC-V: Don't add fractional LMUL types to V_VLS for XTheadVector To: "juzhe.zhong@rivai.ai" Cc: gcc-patches , "Kito.cheng" , palmer , andrew , "philipp.tomsich" , Camel Coder , Bruce Hoult , "cooper.joshua" , "cooper.qu" , jinma Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Mar 22, 2024 at 2:18=E2=80=AFAM juzhe.zhong@rivai.ai wrote: > > LGTM. Pushed. Thanks! > > ________________________________ > juzhe.zhong@rivai.ai > > > From: Christoph M=C3=BCllner > Date: 2024-03-22 07:45 > To: gcc-patches; Kito Cheng; Palmer Dabbelt; Andrew Waterman; Philipp Tom= sich; Camel Coder; Bruce Hoult; Juzhe-Zhong; Jun Sha; Xianmiao Qu; Jin Ma > CC: Christoph M=C3=BCllner > Subject: [PATCH] RISC-V: Don't add fractional LMUL types to V_VLS for XTh= eadVector > The expansion of `memset` (via expand_builtin_memset_args()) > uses clear_by_pieces() and store_by_pieces() to avoid calls > to the C runtime. To check if a type can be used for that purpose > the function by_pieces_mode_supported_p() tests if a `mov` and > a `vec_duplicate` INSN can be expaned by the backend. > > The `vec_duplicate` expansion takes arguments of type `V_VLS`. > The `mov` expansions take arguments of type `V`, `VB`, `VT`, > `VLS_AVL_IMM`, and `VLS_AVL_REG`. Some of these types (in fact > not types but type iterators) include fractional LMUL types. > E.g. `V_VLS` includes `V`, which includes `VI`, which includes > `RVVMF2QI`. > > This results in an attempt to use fractional LMUL-types for > the `memset` expansion resulting in an ICE for XTheadVector, > because that extension cannot handle fractional LMULs. > > This patch addresses this issue by splitting the definition > of the `VI` mode itereator into `VI_NOFRAC` (without fractional > LMUL types) and `VI_FRAC` (only fractional LMUL types). > Further, it defines `V_VLS` such, that `VI_FRAC` types are only > included if XTheadVector is not enabled. > > The effect is demonstrated by a new test case that shows > that the by-pieces framework now emits `sb` instructions > instead of triggering an ICE. > > Signed-off-by: Christoph M=C3=BCllner > > PR 114194 > > gcc/ChangeLog: > > * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC. > Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/rvv/xtheadvector/pr114194.c: New test. > > Signed-off-by: Christoph M=C3=BCllner > --- > gcc/config/riscv/vector-iterators.md | 19 +++++-- > .../riscv/rvv/xtheadvector/pr114194.c | 56 +++++++++++++++++++ > 2 files changed, 69 insertions(+), 6 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr1141= 94.c > > diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vect= or-iterators.md > index c2ea7e8b10a..a24e1bf078f 100644 > --- a/gcc/config/riscv/vector-iterators.md > +++ b/gcc/config/riscv/vector-iterators.md > @@ -108,17 +108,24 @@ (define_c_enum "unspecv" [ > UNSPECV_FRM_RESTORE_EXIT > ]) > -(define_mode_iterator VI [ > - RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MI= N_VLEN > 32") > - > - RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > = 32") > - > - RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32") > +;; Subset of VI with fractional LMUL types > +(define_mode_iterator VI_FRAC [ > + RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32") > + RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32") > + (RVVMF2SI "TARGET_MIN_VLEN > 32") > +]) > +;; Subset of VI with non-fractional LMUL types > +(define_mode_iterator VI_NOFRAC [ > + RVVM8QI RVVM4QI RVVM2QI RVVM1QI > + RVVM8HI RVVM4HI RVVM2HI RVVM1HI > + RVVM8SI RVVM4SI RVVM2SI RVVM1SI > (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64") > (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64") > ]) > +(define_mode_iterator VI [ VI_NOFRAC (VI_FRAC "!TARGET_XTHEADVECTOR") ]) > + > ;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16 > ;; changed to TARGET_ZVFH. TARGET_VECTOR_ELEN_FP_16 is also true for > ;; TARGET_ZVFHMIN while we actually want to disable all instructions apar= t > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c b= /gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c > new file mode 100644 > index 00000000000..fc2d1349425 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c > @@ -0,0 +1,56 @@ > +/* { dg-do compile } */ > +/* { dg-options "-march=3Drv32gc_xtheadvector" { target { rv32 } } } */ > +/* { dg-options "-march=3Drv64gc_xtheadvector" { target { rv64 } } } */ > +/* { dg-final { check-function-bodies "**" "" } } */ > + > +/* > +** foo0_1: > +** sb\tzero,0([a-x0-9]+) > +** ret > +*/ > +void foo0_1 (void *p) > +{ > + __builtin_memset (p, 0, 1); > +} > + > +/* > +** foo0_7: > +** sb\tzero,0([a-x0-9]+) > +** sb\tzero,1([a-x0-9]+) > +** sb\tzero,2([a-x0-9]+) > +** sb\tzero,3([a-x0-9]+) > +** sb\tzero,4([a-x0-9]+) > +** sb\tzero,5([a-x0-9]+) > +** sb\tzero,6([a-x0-9]+) > +** ret > +*/ > +void foo0_7 (void *p) > +{ > + __builtin_memset (p, 0, 7); > +} > + > +/* > +** foo1_1: > +** li\t[a-x0-9]+,1 > +** sb\t[a-x0-9]+,0([a-x0-9]+) > +** ret > +*/ > +void foo1_1 (void *p) > +{ > + __builtin_memset (p, 1, 1); > +} > + > +/* > +** foo1_5: > +** li\t[a-x0-9]+,1 > +** sb\t[a-x0-9]+,0([a-x0-9]+) > +** sb\t[a-x0-9]+,1([a-x0-9]+) > +** sb\t[a-x0-9]+,2([a-x0-9]+) > +** sb\t[a-x0-9]+,3([a-x0-9]+) > +** sb\t[a-x0-9]+,4([a-x0-9]+) > +** ret > +*/ > +void foo1_5 (void *p) > +{ > + __builtin_memset (p, 1, 5); > +} > -- > 2.44.0 > >