From: Phoebe Wang <phoebe.pf.w@gmail.com>
To: Joseph Myers <joseph@codesourcery.com>
Cc: "Wang, Phoebe" <phoebe.wang@intel.com>,
Hongtao Liu <crazylht@gmail.com>,
"Jiang, Haochen" <haochen.jiang@intel.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
"ubizjak@gmail.com" <ubizjak@gmail.com>,
"Liu, Hongtao" <hongtao.liu@intel.com>,
"Zhang, Annita" <annita.zhang@intel.com>,
x86-64-abi <x86-64-abi@googlegroups.com>,
llvm-dev <llvm-dev@lists.llvm.org>,
Craig Topper <craig.topper@gmail.com>
Subject: Re: Intel AVX10.1 Compiler Design and Support
Date: Thu, 10 Aug 2023 20:36:06 +0800 [thread overview]
Message-ID: <CAFSd+HNTTJfS8160ya=Ediwbf0rgk=Dou7JtwdFm8fYXPogLbg@mail.gmail.com> (raw)
In-Reply-To: <8fb470de-d2a3-3e71-be6a-ccc7f4f31a31@codesourcery.com>
[-- Attachment #1: Type: text/plain, Size: 3621 bytes --]
> Changing ABIs like that for existing code that has worked for some time
on
> existing hardware is a bad idea.
I agree, so Proposal 3 is the last choice.
The target of the proposals is to solve the ABI incompatible issue between
AVX10-256 and AVX10-512 when passing/returning 512 vectors. So we are
discussing the default ABI rather than other vector variants.
If you believe that changing 512-bit ABI (the 512-bit version) is a bad
idea, how about Proposal 1 and 2? I don't want to call the non 512-bit
version an ABI because it doesn't provide the interaction between 256-bit
and 512-bit targets. Besides, LLVM also behaves differently with GCC on non
512-bit targets. It is a good time to solve the problem together if we make
the 512-bit ABI consistent and target independent. WDYT?
Thanks
Phoebe
Joseph Myers <joseph@codesourcery.com> 于2023年8月10日周四 04:43写道:
> On Wed, 9 Aug 2023, Wang, Phoebe via Gcc-patches wrote:
>
> > Proposal 3: Change the ABI of 512-bit vector and always be
> > passed/returned from memory.
>
> Changing ABIs like that for existing code that has worked for some time on
> existing hardware is a bad idea.
>
> At this point it seems appropriate to remind people of another ABI
> consideration for vector extensions. glibc's libmvec defines vector
> versions of various functions, including AVX512 ones (of course those
> function versions only work on hardware with the relevant instructions).
> glibc's headers use both _Pragma ("omp declare simd notinbranch") and
> __attribute__ ((__simd__ ("notinbranch"))) to declare, to the compiler
> including those headers, what function variants are available in glibc.
>
> Existing glibc versions need to continue to work with new compiler
> versions. That is, it's part of the ABI, which must remain stable,
> exactly which function versions the above pragma and attribute imply are
> available - and of course the details of how those functions versions take
> arguments / return results are also part of the ABI (it would be OK for a
> new compiler to choose not to use some of those vector versions, but not
> to start calling them with a different ABI).
>
> Maybe you'll want to add new vector function versions, with different
> interfaces, to libmvec in future. If so, you need a *different* pragma or
> attribute to declare to the compiler that the libmvec version using that
> pragma or attribute has the additional functions - so new compilers using
> the existing header will not try to generate calls to new function
> versions that don't exist in that glibc version (but new compilers using a
> new header version from new glibc will see the new pragma or attribute and
> so be able to generate the relevant calls to new functions). And once
> you've defined the ABI for such a new pragma or attribute, that itself
> then becomes a stable interface - so if you end up with vector extensions
> involving yet another set of interfaces, they need another corresponding
> new pragma / attribute for libmvec to declare to the compiler that the new
> interfaces exist.
>
> --
> Joseph S. Myers
> joseph@codesourcery.com
>
> --
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> .
>
next prev parent reply other threads:[~2023-08-10 12:36 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-08 7:13 Haochen Jiang
2023-08-08 7:13 ` [PATCH 1/3] Initial support for AVX10.1 Haochen Jiang
2023-08-16 2:29 ` Hongtao Liu
2023-08-08 7:13 ` [PATCH 2/3] Emit a warning when disabling AVX512 with AVX10 enabled or disabling AVX10 with AVX512 enabled Haochen Jiang
2023-08-16 2:30 ` Hongtao Liu
2023-08-08 7:13 ` [PATCH 3/3] Emit a warning when AVX10 options conflict in vector width Haochen Jiang
2023-08-16 2:30 ` Hongtao Liu
2023-08-08 7:19 ` [PATCH 1/6] Support AVX10.1 for AVX512DQ+AVX512VL intrins Haochen Jiang
2023-08-08 7:20 ` [PATCH 2/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 3/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 4/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 5/6] " Haochen Jiang
2023-08-08 7:20 ` [PATCH 6/6] " Haochen Jiang
2023-08-16 2:36 ` Hongtao Liu
2023-08-08 7:42 ` Intel AVX10.1 Compiler Design and Support Jakub Jelinek
2023-08-08 8:14 ` Jiang, Haochen
2023-08-08 12:44 ` Richard Biener
2023-08-09 2:06 ` Hongtao Liu
2023-08-09 2:08 ` Hongtao Liu
2023-08-09 6:30 ` Jiang, Haochen
2023-08-08 19:55 ` Joseph Myers
2023-08-09 1:21 ` Hongtao Liu
2023-08-09 2:14 ` Hongtao Liu
2023-08-09 2:18 ` Hongtao Liu
2023-08-09 3:59 ` Wang, Phoebe
2023-08-09 20:43 ` Joseph Myers
2023-08-09 20:49 ` Jakub Jelinek
2023-08-10 12:36 ` Phoebe Wang [this message]
2023-08-10 12:45 ` Richard Biener
2023-08-10 13:12 ` Phoebe Wang
2023-08-10 13:30 ` Jan Beulich
2023-08-10 13:52 ` Richard Biener
2023-08-10 14:15 ` Jiang, Haochen
2023-08-10 15:08 ` Zhang, Annita
2023-08-10 15:18 ` Jakub Jelinek
2023-08-10 22:16 ` Joseph Myers
2023-08-09 4:01 ` Phoebe Wang
2023-08-09 5:37 ` Richard Biener
2023-08-09 6:24 ` Jiang, Haochen
2023-08-09 8:14 ` Florian Weimer
2023-08-09 8:24 ` Hongtao Liu
2023-08-09 7:17 ` Jan Beulich
2023-08-09 7:38 ` Hongtao Liu
2023-08-09 8:04 ` Jan Beulich
2023-08-09 9:15 ` Florian Weimer
2023-08-09 10:15 ` Hongtao Liu
2023-08-09 10:17 ` Zhang, Annita
2023-08-09 13:54 ` Michael Matz
2023-08-09 14:34 ` Zhang, Annita
2023-08-10 15:08 ` Jiang, Haochen
2023-08-10 16:00 ` Jakub Jelinek
2023-08-19 22:44 ` ZiNgA BuRgA
2023-08-20 5:44 ` Richard Biener
2023-08-21 1:19 ` Hongtao Liu
2023-08-21 7:36 ` Richard Biener
2023-08-21 8:09 ` Jakub Jelinek
2023-08-21 8:28 ` Hongtao Liu
2023-08-21 8:37 ` Jakub Jelinek
2023-08-21 8:46 ` Hongtao Liu
2023-08-21 9:34 ` Richard Biener
2023-08-21 9:36 ` Richard Biener
2023-08-21 9:50 ` Hongtao Liu
2023-08-21 9:26 ` ZiNgA BuRgA
2023-08-22 3:20 ` Jiang, Haochen
2023-08-22 7:36 ` Richard Biener
2023-08-22 8:34 ` Jakub Jelinek
2023-08-22 8:35 ` Richard Biener
2023-08-22 8:52 ` Jiang, Haochen
2023-08-22 9:23 ` Richard Biener
2023-08-22 13:02 ` Hongtao Liu
2023-08-22 13:16 ` Jakub Jelinek
2023-08-22 13:23 ` Richard Biener
2023-08-22 13:35 ` Hongtao Liu
2023-08-22 13:54 ` Jakub Jelinek
2023-08-22 14:35 ` Hongtao Liu
2023-08-22 15:01 ` Jakub Jelinek
2023-08-23 1:57 ` Jiang, Haochen
2023-08-23 2:19 ` Hongtao Liu
2023-08-23 6:47 ` Jiang, Haochen
2023-08-23 8:16 ` Jakub Jelinek
2023-08-23 8:27 ` Hongtao Liu
2023-08-23 7:32 ` Richard Biener
2023-08-23 8:03 ` Jiang, Haochen
2023-08-23 8:31 ` Jakub Jelinek
2023-08-23 8:47 ` Hongtao Liu
2023-08-23 8:24 ` Hongtao Liu
2023-08-22 14:39 ` Hongtao Liu
2023-08-21 7:49 ` ZiNgA BuRgA
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