From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf33.google.com (mail-qv1-xf33.google.com [IPv6:2607:f8b0:4864:20::f33]) by sourceware.org (Postfix) with ESMTPS id C44DD384B0C3 for ; Fri, 3 Jun 2022 10:23:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C44DD384B0C3 Received: by mail-qv1-xf33.google.com with SMTP id el14so5271109qvb.7 for ; Fri, 03 Jun 2022 03:23:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=CyE/QEk8rnRxbHKbuwmP/42dDx1pi/QwALqNu4RKKKc=; b=PD8q0qJHrhzTLGVPZrwaqRFHV8I2iiBV7ybOBLzqlNQMRBvh93syGhfwEC5UFgg+Ng rNWq6HzOmghZ2YUO7dXGWUalJkqEEd27WExXGzRpq0D8xJg/6uVxYWhLNtdXOAPbCDDP i5PEUzn6tKG8XCOxaaDN4QrY4YtV5UGAOZF4MIb1I5jcEWyWddAEmxq+x/e0BHA8w394 kNVs+yqhT9RpteHF7hjFiv0SwXOjRsia2LsrKovuidLOmaCuwNmpRX/Ue1JcDd9ZJqBa +O/uIIXoEldKGVFoRqZcQJ2+WfKou5QtxQ4ys6kfmQTkZugPaCyn7VGu0cjHrgWkJjf9 F5SQ== X-Gm-Message-State: AOAM530NRhf4WnqgbvFSi4KTlB+1520hbgk+WYOj2hJtV/vEPlwOBCDZ SIuHclDg/K1Q3t+MXPEBj9+GSxAdIwsie9scCAA= X-Google-Smtp-Source: ABdhPJxidrKAzZiLSvU35qQikyOic6pldowYQFEjfzWgeJ8HEEdi1poHCdQrUayZCr+qebVNNGcMCrKQyJuSAMMSHAQ= X-Received: by 2002:a0c:fd6b:0:b0:462:5f5f:9ef with SMTP id k11-20020a0cfd6b000000b004625f5f09efmr40169084qvs.48.1654251827091; Fri, 03 Jun 2022 03:23:47 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Uros Bizjak Date: Fri, 3 Jun 2022 12:23:36 +0200 Message-ID: Subject: Re: [PATCH] i386: Fix up *_doubleword_mask [PR105825] To: Jakub Jelinek Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Jun 2022 10:23:49 -0000 On Fri, Jun 3, 2022 at 12:17 PM Jakub Jelinek wrote: > > Hi! > > My PR105778 patch apparently broke the following testcase. > If the mask has the top relevant bit clear (i.e. we know we are shifting > by 0 to wordsize bits - 1) but doesn't have all the bits below it set, > we emit andsi3 before the shift sequence. When the pattern had :SI > for that operand, that was just fine, but now that it can be also HImode > or for -m64 DImode, we either can use a lowpart or paradoxical subreg to > SImode as the following patch, or we could use a HImode or DImode AND. I think it is better to leave the operation in its natural mode and leave the peephole pass to do its magic, depending on the target. Uros. > Ok for trunk if it passes bootstrap/regtest on x86_64-linux and i686-linux? > > 2022-06-03 Jakub Jelinek > > PR target/105825 > * config/i386/i386.md (*ashl3_doubleword_mask, > *3_doubleword_mask): If top bit of mask is clear, but lower > bits of mask aren't all set and operands[2] doesn't have SImode, > force it to get and use subreg to SImode for andsi3 operand. > > * gcc.dg/pr105825.c: New test. > > --- gcc/config/i386/i386.md.jj 2022-06-02 10:40:00.034660893 +0200 > +++ gcc/config/i386/i386.md 2022-06-03 12:00:39.323292767 +0200 > @@ -11935,6 +11935,11 @@ (define_insn_and_split "*ashl3_doub > != (( * BITS_PER_UNIT) - 1)) > { > rtx tem = gen_reg_rtx (SImode); > + if (GET_MODE (operands[2]) != SImode) > + { > + operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); > + operands[2] = gen_lowpart (SImode, operands[2]); > + } > emit_insn (gen_andsi3 (tem, operands[2], operands[3])); > operands[2] = tem; > } > @@ -12900,6 +12905,11 @@ (define_insn_and_split "*3_do > != (( * BITS_PER_UNIT) - 1)) > { > rtx tem = gen_reg_rtx (SImode); > + if (GET_MODE (operands[2]) != SImode) > + { > + operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); > + operands[2] = gen_lowpart (SImode, operands[2]); > + } > emit_insn (gen_andsi3 (tem, operands[2], operands[3])); > operands[2] = tem; > } > --- gcc/testsuite/gcc.dg/pr105825.c.jj 2022-06-03 12:01:58.008460659 +0200 > +++ gcc/testsuite/gcc.dg/pr105825.c 2022-06-03 12:01:41.259637783 +0200 > @@ -0,0 +1,13 @@ > +/* PR target/105825 */ > +/* { dg-do compile { target int128 } } */ > +/* { dg-options "-O2" } */ > +/* { dg-additional-options "-mavx" { target avx } } */ > + > +__int128 j; > +int i; > + > +void > +foo (void) > +{ > + j <<= __builtin_parityll (i); > +} > > Jakub >