* [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
@ 2021-12-02 8:27 liuhongt
2021-12-02 8:43 ` Hongtao Liu
0 siblings, 1 reply; 8+ messages in thread
From: liuhongt @ 2021-12-02 8:27 UTC (permalink / raw)
To: gcc-patches
The patch helps reload to choose GENENRAL_REGS alternatives for
SSE_FLOAT_MODE and enabled optimization like
- vmovd %xmm0, -4(%rsp)
- movl $1, %eax
- addl -4(%rsp), %eax
+ movd %xmm0, %eax
+ addl $1, %eax
Bootstrapped anf regtested on x86_64-pc-linux-gnu{-m32,} and
x86_64-pc-linux-gnu{-m32\ march=cascadelake,\ -march=cadcadelake}.
No big performace impact is abserved for SPEC2017 on ICX/CLX with both
Ofast -march=native -flto -funroll-loops and -O2 -mtune=generic options.
Ok for trunk?
gcc/ChangeLog:
PR target/95740
* config/i386/i386.c (ix86_preferred_reload_class): Prefer
INT_SSE_REGS for SSE_FLOAT_MODE_P.
* config/i386/i386.h (INT_SSE_CLASS_P): New.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr95740.c: New test.
---
gcc/config/i386/i386.c | 5 +++--
gcc/config/i386/i386.h | 2 ++
gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++
3 files changed, 31 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 80fee627358..977af1c31a7 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -19194,9 +19194,10 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
return NO_REGS;
}
- /* Prefer SSE regs only, if we can use them for math. */
+ /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS,
+ refer to PR95740. */
if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
- return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+ return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
/* Generally when we see PLUS here, it's the function invariant
(plus soft-fp const_int). Which can only be computed into general
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 2fda1e0686e..ec90e47904b 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1283,6 +1283,8 @@ enum reg_class
reg_class_subset_p ((CLASS), FLOAT_REGS)
#define SSE_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), ALL_SSE_REGS)
+#define INT_SSE_CLASS_P(CLASS) \
+ reg_class_subset_p ((CLASS), INT_SSE_REGS)
#define MMX_CLASS_P(CLASS) \
((CLASS) == MMX_REGS)
#define MASK_CLASS_P(CLASS) \
diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
new file mode 100644
index 00000000000..9bc7b862787
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95740.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
+/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
+
+int
+foo (float a)
+{
+ union{
+ int b;
+ float a;}u;
+ u.a = a;
+ return u.b + 1;
+}
+
+long long
+foo1 (double a)
+{
+ union{
+ long long b;
+ double a;}u;
+ u.a = a;
+ return u.b + 1;
+}
--
2.18.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
2021-12-02 8:27 [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class liuhongt
@ 2021-12-02 8:43 ` Hongtao Liu
2021-12-02 10:24 ` Uros Bizjak
0 siblings, 1 reply; 8+ messages in thread
From: Hongtao Liu @ 2021-12-02 8:43 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On Thu, Dec 2, 2021 at 4:27 PM liuhongt <hongtao.liu@intel.com> wrote:
>
> The patch helps reload to choose GENENRAL_REGS alternatives for
> SSE_FLOAT_MODE and enabled optimization like
>
> - vmovd %xmm0, -4(%rsp)
> - movl $1, %eax
> - addl -4(%rsp), %eax
> + movd %xmm0, %eax
> + addl $1, %eax
>
> Bootstrapped anf regtested on x86_64-pc-linux-gnu{-m32,} and
> x86_64-pc-linux-gnu{-m32\ march=cascadelake,\ -march=cadcadelake}.
>
> No big performace impact is abserved for SPEC2017 on ICX/CLX with both
> Ofast -march=native -flto -funroll-loops and -O2 -mtune=generic options.
>
> Ok for trunk?
>
> gcc/ChangeLog:
>
> PR target/95740
> * config/i386/i386.c (ix86_preferred_reload_class): Prefer
> INT_SSE_REGS for SSE_FLOAT_MODE_P.
> * config/i386/i386.h (INT_SSE_CLASS_P): New.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr95740.c: New test.
> ---
> gcc/config/i386/i386.c | 5 +++--
> gcc/config/i386/i386.h | 2 ++
> gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++
> 3 files changed, 31 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 80fee627358..977af1c31a7 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -19194,9 +19194,10 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
> return NO_REGS;
> }
>
> - /* Prefer SSE regs only, if we can use them for math. */
> + /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS,
> + refer to PR95740. */
> if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
> - return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
>
> /* Generally when we see PLUS here, it's the function invariant
> (plus soft-fp const_int). Which can only be computed into general
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 2fda1e0686e..ec90e47904b 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -1283,6 +1283,8 @@ enum reg_class
> reg_class_subset_p ((CLASS), FLOAT_REGS)
> #define SSE_CLASS_P(CLASS) \
> reg_class_subset_p ((CLASS), ALL_SSE_REGS)
> +#define INT_SSE_CLASS_P(CLASS) \
> + reg_class_subset_p ((CLASS), INT_SSE_REGS)
> #define MMX_CLASS_P(CLASS) \
> ((CLASS) == MMX_REGS)
> #define MASK_CLASS_P(CLASS) \
> diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
> new file mode 100644
> index 00000000000..9bc7b862787
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr95740.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
> +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
> +
> +int
> +foo (float a)
> +{
> + union{
> + int b;
> + float a;}u;
> + u.a = a;
> + return u.b + 1;
> +}
> +
> +long long
> +foo1 (double a)
> +{
> + union{
> + long long b;
> + double a;}u;
> + u.a = a;
> + return u.b + 1;
> +}
> --
> 2.18.1
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
2021-12-02 8:43 ` Hongtao Liu
@ 2021-12-02 10:24 ` Uros Bizjak
2021-12-03 6:18 ` liuhongt
0 siblings, 1 reply; 8+ messages in thread
From: Uros Bizjak @ 2021-12-02 10:24 UTC (permalink / raw)
To: Hongtao Liu; +Cc: GCC Patches
On Thu, Dec 2, 2021 at 9:36 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Thu, Dec 2, 2021 at 4:27 PM liuhongt <hongtao.liu@intel.com> wrote:
> >
> > The patch helps reload to choose GENENRAL_REGS alternatives for
> > SSE_FLOAT_MODE and enabled optimization like
> >
> > - vmovd %xmm0, -4(%rsp)
> > - movl $1, %eax
> > - addl -4(%rsp), %eax
> > + movd %xmm0, %eax
> > + addl $1, %eax
> >
> > Bootstrapped anf regtested on x86_64-pc-linux-gnu{-m32,} and
> > x86_64-pc-linux-gnu{-m32\ march=cascadelake,\ -march=cadcadelake}.
> >
> > No big performace impact is abserved for SPEC2017 on ICX/CLX with both
> > Ofast -march=native -flto -funroll-loops and -O2 -mtune=generic options.
> >
> > Ok for trunk?
Please also consider TARGET_INTER_UNIT_MOVES_TO_VEC and
TARGET_INTER_UNIT_MOVES_FROM_VEC.
Uros.
> >
> > gcc/ChangeLog:
> >
> > PR target/95740
> > * config/i386/i386.c (ix86_preferred_reload_class): Prefer
> > INT_SSE_REGS for SSE_FLOAT_MODE_P.
> > * config/i386/i386.h (INT_SSE_CLASS_P): New.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/i386/pr95740.c: New test.
> > ---
> > gcc/config/i386/i386.c | 5 +++--
> > gcc/config/i386/i386.h | 2 ++
> > gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++
> > 3 files changed, 31 insertions(+), 2 deletions(-)
> > create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c
> >
> > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> > index 80fee627358..977af1c31a7 100644
> > --- a/gcc/config/i386/i386.c
> > +++ b/gcc/config/i386/i386.c
> > @@ -19194,9 +19194,10 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
> > return NO_REGS;
> > }
> >
> > - /* Prefer SSE regs only, if we can use them for math. */
> > + /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS,
> > + refer to PR95740. */
> > if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
> > - return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> > + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> >
> > /* Generally when we see PLUS here, it's the function invariant
> > (plus soft-fp const_int). Which can only be computed into general
> > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> > index 2fda1e0686e..ec90e47904b 100644
> > --- a/gcc/config/i386/i386.h
> > +++ b/gcc/config/i386/i386.h
> > @@ -1283,6 +1283,8 @@ enum reg_class
> > reg_class_subset_p ((CLASS), FLOAT_REGS)
> > #define SSE_CLASS_P(CLASS) \
> > reg_class_subset_p ((CLASS), ALL_SSE_REGS)
> > +#define INT_SSE_CLASS_P(CLASS) \
> > + reg_class_subset_p ((CLASS), INT_SSE_REGS)
> > #define MMX_CLASS_P(CLASS) \
> > ((CLASS) == MMX_REGS)
> > #define MASK_CLASS_P(CLASS) \
> > diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
> > new file mode 100644
> > index 00000000000..9bc7b862787
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/i386/pr95740.c
> > @@ -0,0 +1,26 @@
> > +/* { dg-do compile { target { ! ia32 } } } */
> > +/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
> > +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
> > +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
> > +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
> > +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
> > +
> > +int
> > +foo (float a)
> > +{
> > + union{
> > + int b;
> > + float a;}u;
> > + u.a = a;
> > + return u.b + 1;
> > +}
> > +
> > +long long
> > +foo1 (double a)
> > +{
> > + union{
> > + long long b;
> > + double a;}u;
> > + u.a = a;
> > + return u.b + 1;
> > +}
> > --
> > 2.18.1
> >
>
>
> --
> BR,
> Hongtao
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
2021-12-02 10:24 ` Uros Bizjak
@ 2021-12-03 6:18 ` liuhongt
2021-12-03 9:43 ` Uros Bizjak
0 siblings, 1 reply; 8+ messages in thread
From: liuhongt @ 2021-12-03 6:18 UTC (permalink / raw)
To: gcc-patches
Hi:
> Please also consider TARGET_INTER_UNIT_MOVES_TO_VEC and
> TARGET_INTER_UNIT_MOVES_FROM_VEC.
Here's updated patch.
Also honor TARGET_INTER_UNIT_MOVES_TO/FROM_VEC and in
preferred_{,out_}reload_class.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32\ -march=k8,\ -march=k8}.
Ok?
gcc/ChangeLog:
PR target/95740
* config/i386/i386.c (ix86_preferred_output_reload_class):
don't reload integer register to/from sse register when tune
"inter_unit_moves_to/from_vec" is off.
(ix86_preferred_reload_class): Ditto, also prefer
INT_SSE_REGS for SSE_FLOAT_MODE_P.
* config/i386/i386.h (INT_SSE_CLASS_P): New.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr95740.c: New test.
---
gcc/config/i386/i386.c | 32 +++++++++++++++++++++++--
gcc/config/i386/i386.h | 2 ++
gcc/testsuite/gcc.target/i386/pr95740.c | 26 ++++++++++++++++++++
3 files changed, 58 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 80fee627358..5b90c09a0ba 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -19194,9 +19194,24 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
return NO_REGS;
}
- /* Prefer SSE regs only, if we can use them for math. */
+ /* Unless hard register REGNO is known, it is hard to to tell whether a movd
+ instruction will be generated based on MODE and REGCLASS, because for
+ pseudo-registers, even SFmode could be assigned to INTGER_CLASS_P. */
+ if (GENERAL_REG_P (x)
+ && !TARGET_INTER_UNIT_MOVES_TO_VEC
+ && MAYBE_SSE_CLASS_P (regclass))
+ return NO_REGS;
+
+ if (SSE_REG_P (x)
+ && !TARGET_INTER_UNIT_MOVES_FROM_VEC
+ && MAYBE_INTEGER_CLASS_P (regclass))
+ return NO_REGS;
+
+ /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS,
+ MAYBE_SSE_CLASS_P is too broad, for sse math, FLOAT_SSE_REGS,
+ FLOAT_INT_SSE_REGS should be disliked. */
if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
- return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+ return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
/* Generally when we see PLUS here, it's the function invariant
(plus soft-fp const_int). Which can only be computed into general
@@ -19226,6 +19241,19 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
static reg_class_t
ix86_preferred_output_reload_class (rtx x, reg_class_t regclass)
{
+
+ /* Handle movement between integer and sse register like
+ ix86_preferred_reload_class. */
+ if (GENERAL_REG_P (x)
+ && !TARGET_INTER_UNIT_MOVES_TO_VEC
+ && MAYBE_SSE_CLASS_P (regclass))
+ return NO_REGS;
+
+ if (SSE_REG_P (x)
+ && !TARGET_INTER_UNIT_MOVES_FROM_VEC
+ && MAYBE_INTEGER_CLASS_P (regclass))
+ return NO_REGS;
+
/* Restrict the output reload class to the register bank that we are doing
math on. If we would like not to return a subset of CLASS, reject this
alternative: if reload cannot do this, it will still use its choice. */
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 2fda1e0686e..ec90e47904b 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1283,6 +1283,8 @@ enum reg_class
reg_class_subset_p ((CLASS), FLOAT_REGS)
#define SSE_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), ALL_SSE_REGS)
+#define INT_SSE_CLASS_P(CLASS) \
+ reg_class_subset_p ((CLASS), INT_SSE_REGS)
#define MMX_CLASS_P(CLASS) \
((CLASS) == MMX_REGS)
#define MASK_CLASS_P(CLASS) \
diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
new file mode 100644
index 00000000000..9bc7b862787
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95740.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
+/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
+
+int
+foo (float a)
+{
+ union{
+ int b;
+ float a;}u;
+ u.a = a;
+ return u.b + 1;
+}
+
+long long
+foo1 (double a)
+{
+ union{
+ long long b;
+ double a;}u;
+ u.a = a;
+ return u.b + 1;
+}
--
2.18.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
2021-12-03 6:18 ` liuhongt
@ 2021-12-03 9:43 ` Uros Bizjak
0 siblings, 0 replies; 8+ messages in thread
From: Uros Bizjak @ 2021-12-03 9:43 UTC (permalink / raw)
To: liuhongt; +Cc: gcc-patches
On Fri, Dec 3, 2021 at 7:19 AM liuhongt <hongtao.liu@intel.com> wrote:
>
> Hi:
> > Please also consider TARGET_INTER_UNIT_MOVES_TO_VEC and
> > TARGET_INTER_UNIT_MOVES_FROM_VEC.
> Here's updated patch.
>
> Also honor TARGET_INTER_UNIT_MOVES_TO/FROM_VEC and in
> preferred_{,out_}reload_class.
>
> Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32\ -march=k8,\ -march=k8}.
> Ok?
>
> gcc/ChangeLog:
>
> PR target/95740
> * config/i386/i386.c (ix86_preferred_output_reload_class):
> don't reload integer register to/from sse register when tune
> "inter_unit_moves_to/from_vec" is off.
> (ix86_preferred_reload_class): Ditto, also prefer
> INT_SSE_REGS for SSE_FLOAT_MODE_P.
> * config/i386/i386.h (INT_SSE_CLASS_P): New.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr95740.c: New test.
I was thinking about:
--cut here--
@@ -19194,9 +19194,17 @@ ix86_preferred_reload_class (rtx x,
reg_class_t regclass)
return NO_REGS;
}
- /* Prefer SSE regs only, if we can use them for math. */
+ /* Prefer SSE if we can use them for math. Also allow integer regs
+ when moves between register units are cheap. */
if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
- return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+ {
+ if (TARGET_INTER_UNIT_MOVES_FROM_VEC
+ && TARGET_INTER_UNIT_MOVES_TO_VEC
+ && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (word_mode))
+ return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+ else
+ return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+ }
/* Generally when we see PLUS here, it's the function invariant
(plus soft-fp const_int). Which can only be computed into general
--cut here--
So, INT_SSE class is allowed when interunit moves are enabled. The
patch also takes care for 64-bit moves which are expensive on 32-bit
targets.
Uros.
> ---
> gcc/config/i386/i386.c | 32 +++++++++++++++++++++++--
> gcc/config/i386/i386.h | 2 ++
> gcc/testsuite/gcc.target/i386/pr95740.c | 26 ++++++++++++++++++++
> 3 files changed, 58 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 80fee627358..5b90c09a0ba 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -19194,9 +19194,24 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
> return NO_REGS;
> }
>
> - /* Prefer SSE regs only, if we can use them for math. */
> + /* Unless hard register REGNO is known, it is hard to to tell whether a movd
> + instruction will be generated based on MODE and REGCLASS, because for
> + pseudo-registers, even SFmode could be assigned to INTGER_CLASS_P. */
> + if (GENERAL_REG_P (x)
> + && !TARGET_INTER_UNIT_MOVES_TO_VEC
> + && MAYBE_SSE_CLASS_P (regclass))
> + return NO_REGS;
> +
> + if (SSE_REG_P (x)
> + && !TARGET_INTER_UNIT_MOVES_FROM_VEC
> + && MAYBE_INTEGER_CLASS_P (regclass))
> + return NO_REGS;
> +
> + /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS,
> + MAYBE_SSE_CLASS_P is too broad, for sse math, FLOAT_SSE_REGS,
> + FLOAT_INT_SSE_REGS should be disliked. */
> if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
> - return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
>
> /* Generally when we see PLUS here, it's the function invariant
> (plus soft-fp const_int). Which can only be computed into general
> @@ -19226,6 +19241,19 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
> static reg_class_t
> ix86_preferred_output_reload_class (rtx x, reg_class_t regclass)
> {
> +
> + /* Handle movement between integer and sse register like
> + ix86_preferred_reload_class. */
> + if (GENERAL_REG_P (x)
> + && !TARGET_INTER_UNIT_MOVES_TO_VEC
> + && MAYBE_SSE_CLASS_P (regclass))
> + return NO_REGS;
> +
> + if (SSE_REG_P (x)
> + && !TARGET_INTER_UNIT_MOVES_FROM_VEC
> + && MAYBE_INTEGER_CLASS_P (regclass))
> + return NO_REGS;
> +
> /* Restrict the output reload class to the register bank that we are doing
> math on. If we would like not to return a subset of CLASS, reject this
> alternative: if reload cannot do this, it will still use its choice. */
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 2fda1e0686e..ec90e47904b 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -1283,6 +1283,8 @@ enum reg_class
> reg_class_subset_p ((CLASS), FLOAT_REGS)
> #define SSE_CLASS_P(CLASS) \
> reg_class_subset_p ((CLASS), ALL_SSE_REGS)
> +#define INT_SSE_CLASS_P(CLASS) \
> + reg_class_subset_p ((CLASS), INT_SSE_REGS)
> #define MMX_CLASS_P(CLASS) \
> ((CLASS) == MMX_REGS)
> #define MASK_CLASS_P(CLASS) \
> diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
> new file mode 100644
> index 00000000000..9bc7b862787
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr95740.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
> +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
> +
> +int
> +foo (float a)
> +{
> + union{
> + int b;
> + float a;}u;
> + u.a = a;
> + return u.b + 1;
> +}
> +
> +long long
> +foo1 (double a)
> +{
> + union{
> + long long b;
> + double a;}u;
> + u.a = a;
> + return u.b + 1;
> +}
> --
> 2.18.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
2021-12-06 3:41 liuhongt
2021-12-06 3:44 ` Hongtao Liu
@ 2021-12-06 8:14 ` Uros Bizjak
1 sibling, 0 replies; 8+ messages in thread
From: Uros Bizjak @ 2021-12-06 8:14 UTC (permalink / raw)
To: liuhongt; +Cc: gcc-patches
On Mon, Dec 6, 2021 at 4:41 AM liuhongt via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> When moves between integer and sse registers are cheap.
>
> 2021-12-06 Hongtao Liu <Hongtao.liu@intel.com>
> Uroš Bizjak <ubizjak@gmail.com>
> gcc/ChangeLog:
>
> PR target/95740
> * config/i386/i386.c (ix86_preferred_reload_class): Allow
> integer regs when moves between register units are cheap.
> * config/i386/i386.h (INT_SSE_CLASS_P): New.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr95740.c: New test.
OK.
Thanks,
Uros.
> ---
> gcc/config/i386/i386.c | 12 ++++++++++--
> gcc/config/i386/i386.h | 2 ++
> gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++
> 3 files changed, 38 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 80fee627358..e3c2e294988 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -19194,9 +19194,17 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
> return NO_REGS;
> }
>
> - /* Prefer SSE regs only, if we can use them for math. */
> + /* Prefer SSE if we can use them for math. Also allow integer regs
> + when moves between register units are cheap. */
> if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
> - return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + {
> + if (TARGET_INTER_UNIT_MOVES_FROM_VEC
> + && TARGET_INTER_UNIT_MOVES_TO_VEC
> + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (word_mode))
> + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + else
> + return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + }
>
> /* Generally when we see PLUS here, it's the function invariant
> (plus soft-fp const_int). Which can only be computed into general
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 2fda1e0686e..ec90e47904b 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -1283,6 +1283,8 @@ enum reg_class
> reg_class_subset_p ((CLASS), FLOAT_REGS)
> #define SSE_CLASS_P(CLASS) \
> reg_class_subset_p ((CLASS), ALL_SSE_REGS)
> +#define INT_SSE_CLASS_P(CLASS) \
> + reg_class_subset_p ((CLASS), INT_SSE_REGS)
> #define MMX_CLASS_P(CLASS) \
> ((CLASS) == MMX_REGS)
> #define MASK_CLASS_P(CLASS) \
> diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
> new file mode 100644
> index 00000000000..7ecd71ba8c1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr95740.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-msse2 -O2 -mtune=generic -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
> +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
> +
> +int
> +foo (float a)
> +{
> + union{
> + int b;
> + float a;}u;
> + u.a = a;
> + return u.b + 1;
> +}
> +
> +long long
> +foo1 (double a)
> +{
> + union{
> + long long b;
> + double a;}u;
> + u.a = a;
> + return u.b + 1;
> +}
> --
> 2.18.2
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
2021-12-06 3:41 liuhongt
@ 2021-12-06 3:44 ` Hongtao Liu
2021-12-06 8:14 ` Uros Bizjak
1 sibling, 0 replies; 8+ messages in thread
From: Hongtao Liu @ 2021-12-06 3:44 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
Forget --in-reply-to when git send-email.
> I was thinking about:
>
> --cut here--
> @@ -19194,9 +19194,17 @@ ix86_preferred_reload_class (rtx x,
> reg_class_t regclass)
> return NO_REGS;
> }
>
> - /* Prefer SSE regs only, if we can use them for math. */
> + /* Prefer SSE if we can use them for math. Also allow integer regs
> + when moves between register units are cheap. */
> if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
> - return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + {
> + if (TARGET_INTER_UNIT_MOVES_FROM_VEC
> + && TARGET_INTER_UNIT_MOVES_TO_VEC
> + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (word_mode))
> + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + else
> + return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + }
>
> /* Generally when we see PLUS here, it's the function invariant
> (plus soft-fp const_int). Which can only be computed into general
> --cut here--
>
> So, INT_SSE class is allowed when interunit moves are enabled. The
> patch also takes care for 64-bit moves which are expensive on 32-bit
> targets.
I like your version, update patch.
Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} w/ and w/o -march=k8.
On Mon, Dec 6, 2021 at 11:41 AM liuhongt <hongtao.liu@intel.com> wrote:
>
> When moves between integer and sse registers are cheap.
>
> 2021-12-06 Hongtao Liu <Hongtao.liu@intel.com>
> Uroš Bizjak <ubizjak@gmail.com>
> gcc/ChangeLog:
>
> PR target/95740
> * config/i386/i386.c (ix86_preferred_reload_class): Allow
> integer regs when moves between register units are cheap.
> * config/i386/i386.h (INT_SSE_CLASS_P): New.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/i386/pr95740.c: New test.
> ---
> gcc/config/i386/i386.c | 12 ++++++++++--
> gcc/config/i386/i386.h | 2 ++
> gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++
> 3 files changed, 38 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index 80fee627358..e3c2e294988 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -19194,9 +19194,17 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
> return NO_REGS;
> }
>
> - /* Prefer SSE regs only, if we can use them for math. */
> + /* Prefer SSE if we can use them for math. Also allow integer regs
> + when moves between register units are cheap. */
> if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
> - return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + {
> + if (TARGET_INTER_UNIT_MOVES_FROM_VEC
> + && TARGET_INTER_UNIT_MOVES_TO_VEC
> + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (word_mode))
> + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + else
> + return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
> + }
>
> /* Generally when we see PLUS here, it's the function invariant
> (plus soft-fp const_int). Which can only be computed into general
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 2fda1e0686e..ec90e47904b 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -1283,6 +1283,8 @@ enum reg_class
> reg_class_subset_p ((CLASS), FLOAT_REGS)
> #define SSE_CLASS_P(CLASS) \
> reg_class_subset_p ((CLASS), ALL_SSE_REGS)
> +#define INT_SSE_CLASS_P(CLASS) \
> + reg_class_subset_p ((CLASS), INT_SSE_REGS)
> #define MMX_CLASS_P(CLASS) \
> ((CLASS) == MMX_REGS)
> #define MASK_CLASS_P(CLASS) \
> diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
> new file mode 100644
> index 00000000000..7ecd71ba8c1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr95740.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-msse2 -O2 -mtune=generic -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
> +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
> +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
> +
> +int
> +foo (float a)
> +{
> + union{
> + int b;
> + float a;}u;
> + u.a = a;
> + return u.b + 1;
> +}
> +
> +long long
> +foo1 (double a)
> +{
> + union{
> + long long b;
> + double a;}u;
> + u.a = a;
> + return u.b + 1;
> +}
> --
> 2.18.2
>
--
BR,
Hongtao
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class.
@ 2021-12-06 3:41 liuhongt
2021-12-06 3:44 ` Hongtao Liu
2021-12-06 8:14 ` Uros Bizjak
0 siblings, 2 replies; 8+ messages in thread
From: liuhongt @ 2021-12-06 3:41 UTC (permalink / raw)
To: gcc-patches
When moves between integer and sse registers are cheap.
2021-12-06 Hongtao Liu <Hongtao.liu@intel.com>
Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/95740
* config/i386/i386.c (ix86_preferred_reload_class): Allow
integer regs when moves between register units are cheap.
* config/i386/i386.h (INT_SSE_CLASS_P): New.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr95740.c: New test.
---
gcc/config/i386/i386.c | 12 ++++++++++--
gcc/config/i386/i386.h | 2 ++
gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++
3 files changed, 38 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 80fee627358..e3c2e294988 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -19194,9 +19194,17 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass)
return NO_REGS;
}
- /* Prefer SSE regs only, if we can use them for math. */
+ /* Prefer SSE if we can use them for math. Also allow integer regs
+ when moves between register units are cheap. */
if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
- return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+ {
+ if (TARGET_INTER_UNIT_MOVES_FROM_VEC
+ && TARGET_INTER_UNIT_MOVES_TO_VEC
+ && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (word_mode))
+ return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+ else
+ return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
+ }
/* Generally when we see PLUS here, it's the function invariant
(plus soft-fp const_int). Which can only be computed into general
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 2fda1e0686e..ec90e47904b 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1283,6 +1283,8 @@ enum reg_class
reg_class_subset_p ((CLASS), FLOAT_REGS)
#define SSE_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), ALL_SSE_REGS)
+#define INT_SSE_CLASS_P(CLASS) \
+ reg_class_subset_p ((CLASS), INT_SSE_REGS)
#define MMX_CLASS_P(CLASS) \
((CLASS) == MMX_REGS)
#define MASK_CLASS_P(CLASS) \
diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c
new file mode 100644
index 00000000000..7ecd71ba8c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr95740.c
@@ -0,0 +1,26 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-msse2 -O2 -mtune=generic -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */
+/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */
+/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */
+
+int
+foo (float a)
+{
+ union{
+ int b;
+ float a;}u;
+ u.a = a;
+ return u.b + 1;
+}
+
+long long
+foo1 (double a)
+{
+ union{
+ long long b;
+ double a;}u;
+ u.a = a;
+ return u.b + 1;
+}
--
2.18.2
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-12-06 8:15 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-02 8:27 [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class liuhongt
2021-12-02 8:43 ` Hongtao Liu
2021-12-02 10:24 ` Uros Bizjak
2021-12-03 6:18 ` liuhongt
2021-12-03 9:43 ` Uros Bizjak
2021-12-06 3:41 liuhongt
2021-12-06 3:44 ` Hongtao Liu
2021-12-06 8:14 ` Uros Bizjak
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