From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by sourceware.org (Postfix) with ESMTPS id C66E43858D28 for ; Thu, 2 Dec 2021 10:24:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C66E43858D28 Received: by mail-qv1-xf30.google.com with SMTP id u16so24478751qvk.4 for ; Thu, 02 Dec 2021 02:24:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=awEttp8WI9PBcd5Capnz5Y9grzFnIc0DXrqUyHc9Amw=; b=SkCHNEMUKU21HmO+GDPr7T31qWPOmVSEYr/7yk02Wf4Pgd0zOIgdaXy7eFoNtuJymC Hjaq2rqN8FBbppwyyCJe1WOVjQu/ClnOOdxRgjXAtkRWO5emRA/nk/oSxk5XNE/mY6dH hrwD/OTTa7HumPPnVs7wgF26mNjpELOKg1f6DMpyuOh5Ju5lSqsyuqUqoqv3D4w1r8Ox 4wthhWuY7Mvl/JpBeFbLMMIicSjkL1rZ2toSPV1dgWyqQa0gL4uuNZttWV7DHCGdffrJ KWvpVjD8BE0mjUa9hp5yqEWTWdI38g7cVgYDc48ah0ID41g5ALOhpXEKRiXxVwJI32hV R4SA== X-Gm-Message-State: AOAM531n1yIQLTZ2ibq/CG+1cFiXSzt/8B6MMAUKvg9EVb+5M+ewYYYp kAMTCu26UwJGYF+vOt22UWnzLfOIjFltq6BixsfwoAVqj7Y= X-Google-Smtp-Source: ABdhPJzyboh8eg18AO6nJbk0wdl+WqFor46D8b5dYrbm3bUijpYXblmfx0OuEXF+IVh+IBSrGcD3l9rt4yZP0JnSoPQ= X-Received: by 2002:a05:6214:20ab:: with SMTP id 11mr12036597qvd.31.1638440696262; Thu, 02 Dec 2021 02:24:56 -0800 (PST) MIME-Version: 1.0 References: <20211202082752.62388-1-hongtao.liu@intel.com> In-Reply-To: From: Uros Bizjak Date: Thu, 2 Dec 2021 11:24:44 +0100 Message-ID: Subject: Re: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class. To: Hongtao Liu Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Dec 2021 10:24:58 -0000 On Thu, Dec 2, 2021 at 9:36 AM Hongtao Liu wrote: > > On Thu, Dec 2, 2021 at 4:27 PM liuhongt wrote: > > > > The patch helps reload to choose GENENRAL_REGS alternatives for > > SSE_FLOAT_MODE and enabled optimization like > > > > - vmovd %xmm0, -4(%rsp) > > - movl $1, %eax > > - addl -4(%rsp), %eax > > + movd %xmm0, %eax > > + addl $1, %eax > > > > Bootstrapped anf regtested on x86_64-pc-linux-gnu{-m32,} and > > x86_64-pc-linux-gnu{-m32\ march=cascadelake,\ -march=cadcadelake}. > > > > No big performace impact is abserved for SPEC2017 on ICX/CLX with both > > Ofast -march=native -flto -funroll-loops and -O2 -mtune=generic options. > > > > Ok for trunk? Please also consider TARGET_INTER_UNIT_MOVES_TO_VEC and TARGET_INTER_UNIT_MOVES_FROM_VEC. Uros. > > > > gcc/ChangeLog: > > > > PR target/95740 > > * config/i386/i386.c (ix86_preferred_reload_class): Prefer > > INT_SSE_REGS for SSE_FLOAT_MODE_P. > > * config/i386/i386.h (INT_SSE_CLASS_P): New. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/i386/pr95740.c: New test. > > --- > > gcc/config/i386/i386.c | 5 +++-- > > gcc/config/i386/i386.h | 2 ++ > > gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++ > > 3 files changed, 31 insertions(+), 2 deletions(-) > > create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c > > > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > > index 80fee627358..977af1c31a7 100644 > > --- a/gcc/config/i386/i386.c > > +++ b/gcc/config/i386/i386.c > > @@ -19194,9 +19194,10 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass) > > return NO_REGS; > > } > > > > - /* Prefer SSE regs only, if we can use them for math. */ > > + /* Prefer INT_SSE_REGS, enable reload from SSE register to GENERAL_REGS, > > + refer to PR95740. */ > > if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) > > - return SSE_CLASS_P (regclass) ? regclass : NO_REGS; > > + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS; > > > > /* Generally when we see PLUS here, it's the function invariant > > (plus soft-fp const_int). Which can only be computed into general > > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h > > index 2fda1e0686e..ec90e47904b 100644 > > --- a/gcc/config/i386/i386.h > > +++ b/gcc/config/i386/i386.h > > @@ -1283,6 +1283,8 @@ enum reg_class > > reg_class_subset_p ((CLASS), FLOAT_REGS) > > #define SSE_CLASS_P(CLASS) \ > > reg_class_subset_p ((CLASS), ALL_SSE_REGS) > > +#define INT_SSE_CLASS_P(CLASS) \ > > + reg_class_subset_p ((CLASS), INT_SSE_REGS) > > #define MMX_CLASS_P(CLASS) \ > > ((CLASS) == MMX_REGS) > > #define MASK_CLASS_P(CLASS) \ > > diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c > > new file mode 100644 > > index 00000000000..9bc7b862787 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/i386/pr95740.c > > @@ -0,0 +1,26 @@ > > +/* { dg-do compile { target { ! ia32 } } } */ > > +/* { dg-options "-msse2 -O2 -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */ > > +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */ > > +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */ > > +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */ > > +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */ > > + > > +int > > +foo (float a) > > +{ > > + union{ > > + int b; > > + float a;}u; > > + u.a = a; > > + return u.b + 1; > > +} > > + > > +long long > > +foo1 (double a) > > +{ > > + union{ > > + long long b; > > + double a;}u; > > + u.a = a; > > + return u.b + 1; > > +} > > -- > > 2.18.1 > > > > > -- > BR, > Hongtao