From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by sourceware.org (Postfix) with ESMTPS id 78F833858CDB for ; Tue, 9 Jan 2024 10:19:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 78F833858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 78F833858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::531 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704795568; cv=none; b=QxFKeD+Gp9YJ6bQx4vHbRZYHKT5jlFb3f3geSi6bK1PgNmaJs8UTHvRO9TPxFSnoT1ZeFt6r8pAv04VQzDRf1iCUnUNfFyWpim1mXvm7nRZyyO+5VmLqcmTC4CFh6cAGjg88vTB7PMg3UYeXJZTk1ubF04CVL79siBALXEwdHgc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1704795568; c=relaxed/simple; bh=OBKmqhWrH9HlEeEj0QjYtMHBCQwwKD8HBFVv3s//FGI=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=aXRxZMUoC/ADKWfLV1i6tMNnLzdmEdfiGFKj9BEFMl3JwGqGSbXpcZLqM7ZP0SZZzKXL8k4g/ofu8M/opY/zKMCRKuNBvVsIDusMUYtuZw1/ixUGzibVJ/ciwMISrreGhVIH2X9OSckFLA9rx9ci65i8SvSilnz24K1tRYKYIbw= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-55719cdc0e1so3108666a12.1 for ; Tue, 09 Jan 2024 02:19:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1704795565; x=1705400365; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=IfuB7nYvzXL2k+Xr6Y16UAHv/aCGNek+bQ91bI6kQbU=; b=MYPsCvtybqz94SlzJoQ9lIlp1UAUvrDiz4nCk+ciBirpiEL7XmOsHHh85UyE3F9iuQ 0AbAE9sLnfXAvtzrtZ8G1gMb22BHZgLckLstV3iiKvGRKfDczWMYB9W8mGo7z9BZr6ll wHqS5Zxq/MVqTn+d5YWlWB4ZT0dBo3lsrx4eRgBuLW+qfGS8iI14AvTW5YnUDRXHl1Sg 8jwKj6uUHsoHZJN8FdT3UKlBL90jqJJoS1Rgb5GyZhjInixozX6zZYPQRFliizigXcZt VM0NXRwqDnZFv1QUY5Mo9c4PNaqYl4xMRTG0daVCCTmynNOoRVVNKoe3JVGTebTyPvp2 X8Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704795565; x=1705400365; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IfuB7nYvzXL2k+Xr6Y16UAHv/aCGNek+bQ91bI6kQbU=; b=gpocndn9yuwPR0qnqREYNWGRSRMiQ1qnRoOdkyOztw4i3GE45bcmTAYDy7vbr2a4rc Ew5EYAfFXtzkry6mr/kBHk0s2AYQQQviFk6H5XNrtpzcz2dt83RHoc5M++eCIWeMv+UH Ce0j3zE/NUmfAQOF2K0pr8RJ5k4jRJHejt2AIgp03JgLILkz5pMmNoBRz978Fpsvy7DC WsGvKuwpYxbCpDKqKPOOtCNbC/iIUn4FK91k5JoY2oIERyly+dsOHktgeZHj5hC3QR4n 3BTY3d4USujWGN3zY1ju+HFjv0CNQj+HFe5Xv15MGEhEzrl3CrXp9OqzztWoJImLgRVn BM+A== X-Gm-Message-State: AOJu0Ywn8/Q97q9KbcBaMOMcLI5oJ1ftUJi8rwLklqSMD3ABWWPB3fNk IsxUXF9q0yY4CKc87Ast7Ttd0NqEH3gvL4eFMqJv+coorGk= X-Google-Smtp-Source: AGHT+IG/bAMNUJnlTuthV7cjFlTPvjk1ZLuB/n8WG7QnE9DaFsLWIf1PTDqHxX48yNiRwmasIGvpnKGpG+HvnFYqRjY= X-Received: by 2002:a50:ccd7:0:b0:553:a9cc:b337 with SMTP id b23-20020a50ccd7000000b00553a9ccb337mr2975636edj.41.1704795564991; Tue, 09 Jan 2024 02:19:24 -0800 (PST) MIME-Version: 1.0 References: <69pn947p-0q52-1snr-8267-094n4n541r03@fhfr.qr> In-Reply-To: From: Uros Bizjak Date: Tue, 9 Jan 2024 11:19:14 +0100 Message-ID: Subject: Re: [PATCH] match.pd: Convert {I, X}OR of two values ANDed with alien CSTs to PLUS [PR108477] To: Richard Biener Cc: Andrew Pinski , "gcc-patches@gcc.gnu.org" , Jeff Law Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Tue, Jan 9, 2024 at 11:06=E2=80=AFAM Richard Biener = wrote: > > On Tue, 9 Jan 2024, Uros Bizjak wrote: > > > On Tue, Jan 9, 2024 at 10:44?AM Richard Biener wrot= e: > > > > > > On Tue, 9 Jan 2024, Uros Bizjak wrote: > > > > > > > On Tue, Jan 9, 2024 at 9:58?AM Richard Biener w= rote: > > > > > > > > > > On Mon, 8 Jan 2024, Uros Bizjak wrote: > > > > > > > > > > > On Mon, Jan 8, 2024 at 5:57?PM Andrew Pinski wrote: > > > > > > > > > > > > > > On Mon, Jan 8, 2024 at 6:44?AM Uros Bizjak wrote: > > > > > > > > > > > > > > > > Instead of converting XOR or PLUS of two values, ANDed with= two constants that > > > > > > > > have no bits in common, to IOR expression, convert IOR or X= OR of said two > > > > > > > > ANDed values to PLUS expression. > > > > > > > > > > > > > > I think this only helps targets which have leal like instruct= ion. Also > > > > > > > I think it is the same issue as I recorded as PR 111763 . I = suspect > > > > > > > BIT_IOR is more of a Canonical form for GIMPLE while we shoul= d handle > > > > > > > this in expand to decide if we want to use PLUS or IOR. > > > > > > > > > > > > For the pr108477.c testcase, expand pass expands: > > > > > > > > > > > > r_3 =3D a_2(D) & 1; > > > > > > p_5 =3D b_4(D) & 4294967292; > > > > > > _1 =3D r_3 | p_5; > > > > > > _6 =3D _1 + 2; > > > > > > return _6; > > > > > > > > > > > > The transformation ( | -> + ) is valid only when CST1 & CST2 = =3D=3D 0, so > > > > > > we need to determine values of constants. Is this information > > > > > > available in the expand pass? > > > > > > > > > > If there's single-uses then TER makes this info available. > > > > > > > > > > > IMO, the transformation from (ra | rb | cst) to (ra + rb + cst)= as in > > > > > > the shown testcase would be beneficial when constructing contro= l > > > > > > register values (see e.g. mesa-3d). We can use LEA instead of O= R+ADD > > > > > > sequence in this case. > > > > > > > > > > The other possibility is to expose LEA as optab and making GIMPLE > > > > > instruction selection generate a direct internal function for tha= t > > > > > (that would be the "better" way). There is LEA-like &TARGET_MEM_= REF > > > > > but that has constraints on the addends mode (ptr_mode) which mig= ht > > > > > not fit what the target can do? Otherwise that would be an exist= ing > > > > > way to do this computation as well. > > > > > > > > I think there is no need for a new optab. If we can determine at > > > > expand time that ANDed values are fed to the IOR/XOR expressions, t= hen > > > > we can check the constants and emit PLUS RTX instead. RTL combine p= ass > > > > will then create LEA instruction from separate PLUS instructions. > > > > > > > > So, we can emit: > > > > > > > > op0 =3D and (a, CST1) > > > > op1 =3D and (b, CST2) > > > > op2 =3D plus (op0, op1) > > > > > > > > RTX sequence for (a & CST1) | (b & CST2) when CST1 & CST2 =3D=3D 0 > > > > > > > > and > > > > > > > > op0 =3D and (a, CST1) > > > > op1 =3D plus (op0, CST2) > > > > > > > > RTX sequence for (a & CST1) | CST2 when CST1 & CST2 =3D=3D 0 > > > > > > > > The above transformation is valid for IOR and XOR. > > > > > > > > x86 can't combine IOR/XOR in any meaningful way, but can combine th= e > > > > sequence of PLUS (together with MULT) RTXes to LEA. > > > > > > Btw, this looks like a three-insn combination even with IOR so a > > > pattern for this case would work as well? > > > > IIUC the question: x86 does not have three-input IOR, but we want to > > emulate it with LEA (three-input PLUS, but one of the arguments has to > > be constant). > > But couldn't you have a define_insn matching LEA but with IOR instead > of PLUS (and with the appropriate constraints?). Maybe it could > also be combine trying PLUS instead of IOR if that's possible > (looking at the constants). we would have to include masking ANDs in the define_insn and add additional conditions regarding mask constants in the insn constraint. So, this define_insn would look something like: (ior (ior (and (op1, CST1), and (op2, CST2)), CST3)) with (CST1 & CST2 & CST3) =3D=3D 0 condition. and combinations with PLUS / MULT RTXes including all the variants with two arguments. Uros.