From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14939 invoked by alias); 30 Dec 2012 13:21:23 -0000 Received: (qmail 14920 invoked by uid 22791); 30 Dec 2012 13:21:21 -0000 X-SWARE-Spam-Status: No, hits=-5.0 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,KHOP_RCVD_TRUST,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE,TW_AV,TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-oa0-f51.google.com (HELO mail-oa0-f51.google.com) (209.85.219.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 30 Dec 2012 13:21:15 +0000 Received: by mail-oa0-f51.google.com with SMTP id n12so10971638oag.24 for ; Sun, 30 Dec 2012 05:21:14 -0800 (PST) MIME-Version: 1.0 Received: by 10.182.212.2 with SMTP id ng2mr31376846obc.81.1356873674467; Sun, 30 Dec 2012 05:21:14 -0800 (PST) Received: by 10.182.153.201 with HTTP; Sun, 30 Dec 2012 05:21:14 -0800 (PST) In-Reply-To: References: Date: Sun, 30 Dec 2012 13:21:00 -0000 Message-ID: Subject: Re: [RFC, x86] Changes for AVX and AVX2 processors From: Uros Bizjak To: Vladimir Yakovlev Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-12/txt/msg01479.txt.bz2 On Sat, Dec 29, 2012 at 5:57 PM, Vladimir Yakovlev wrote: > I did changes. Please take a look. > > 2012/12/29, Uros Bizjak : >> On Sat, Dec 29, 2012 at 6:26 AM, Vladimir Yakovlev >> wrote: >> >>> processor_alias_table contains the same processor type for all >>> "corei7", "corei7-avx", "core-avx-i" and "core-avx2". At least, it has >>> consequence on checking x86_avx256_split_unaligned_load & >>> ix86_tune_mask: for all these processors it results the same. Moreover >>> we cannot turn new features on for AVX/AVX2 using >>> initial_ix86_tune_features. >> >> corei7, corei7-avx and core-avx-i are all based on sandybridge (= >> PROCESSOR_COREI7) architecture. The only problematic entry is >> core-avx2, which should be based on new architecture. I propose >> PROCESSOR_HASWELL, in the same way as we have PROCESSOR_NOCONA. @@ -2467,6 +2470,7 @@ "nocona", "core2", "corei7", + "coreavx2", "atom", "geode", "k6", This string should match processor_alias_table name, so "core-avx2". @@ -28709,6 +28716,10 @@ arg_str = "corei7"; priority = P_PROC_SSE4_2; break; + case PROCESSOR_HASWELL: + arg_str = "core_avx2"; + priority = P_PROC_SSE4_2; + break; case PROCESSOR_ATOM: arg_str = "atom"; priority = P_PROC_SSSE3; This is part of a processor dispatcher functionality. To support this functionality, some more changes are needed, so it is IMO best to leave this part out for now. I would also like the author of processor dispatcher to review changes in this area. On a related note, it looks to me that corei7 should declare P_PROC_AVX here (this change should be part of another patch). Other than that , the patch looks OK, but please repost final version with a correct ChangeLog. Uros.