From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 64231 invoked by alias); 10 Feb 2019 11:20:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 64221 invoked by uid 89); 10 Feb 2019 11:20:55 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-it1-f193.google.com Received: from mail-it1-f193.google.com (HELO mail-it1-f193.google.com) (209.85.166.193) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 10 Feb 2019 11:20:54 +0000 Received: by mail-it1-f193.google.com with SMTP id a6so19594859itl.4 for ; Sun, 10 Feb 2019 03:20:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=BA5GWjGo/ZzmWbHyUN/0rHXuFmM4SXA/oY/XsbB1clE=; b=WC4CYjQDfU90zuWhWNydnin4tkKvwjoDc3d0TsdpOKyPaYOaQBDWslYsoU+vYAYgkY mjjpLyoxPEym/JZ6N7cvcFCX4TXcncmi1r08sVR3RHq+wlXi55+WHER5Miy0gSAH/UKr QtXBTVRkea5cnUpphdPdgDtlhQrCBqkqY6McgoJAtQLZ9Dx4IAHtEpvhXEdzhmHZ1z7Q QxxKxH3HHxf7rAEYW0VWQTSHlb+tf0gmowzmzglULiFhsZjjZrOltsOkOaecqEjdeCxn R3kSnrEjQXGeGgP3GPuu+FGtLmhoI+GXeotKhTzhzYzW+UeQhktu2ex9jwK93u2sG/pv q/UA== MIME-Version: 1.0 Received: by 2002:a05:6638:393:0:0:0:0 with HTTP; Sun, 10 Feb 2019 03:20:52 -0800 (PST) In-Reply-To: <20190210001947.27278-17-hjl.tools@gmail.com> References: <20190210001947.27278-1-hjl.tools@gmail.com> <20190210001947.27278-17-hjl.tools@gmail.com> From: Uros Bizjak Date: Sun, 10 Feb 2019 11:20:00 -0000 Message-ID: Subject: Re: [PATCH 16/43] i386: Emulate MMX mmx_pextrw with SSE To: "H.J. Lu" Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2019-02/txt/msg00661.txt.bz2 On 2/10/19, H.J. Lu wrote: > Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is > allowed. > > PR target/89021 > * config/i386/mmx.md (mmx_pextrw): Add SSE emulation. > --- > gcc/config/i386/mmx.md | 16 +++++++++------- > 1 file changed, 9 insertions(+), 7 deletions(-) > > diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md > index dc81d7f45df..57669018d0c 100644 > --- a/gcc/config/i386/mmx.md > +++ b/gcc/config/i386/mmx.md > @@ -1349,16 +1349,18 @@ > (set_attr "mode" "DI")]) > > (define_insn "mmx_pextrw" > - [(set (match_operand:SI 0 "register_operand" "=r") > + [(set (match_operand:SI 0 "register_operand" "=r,r") > (zero_extend:SI > (vec_select:HI > - (match_operand:V4HI 1 "register_operand" "y") > - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))] > - "TARGET_SSE || TARGET_3DNOW_A" > - "pextrw\t{%2, %1, %0|%0, %1, %2}" > - [(set_attr "type" "mmxcvt") > + (match_operand:V4HI 1 "register_operand" "y,Yv") > + (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))] > + "((TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSE) > + || TARGET_3DNOW_A" (TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A) Uros. > + "%vpextrw\t{%2, %1, %0|%0, %1, %2}" > + [(set_attr "mmx_isa" "native,x64") > + (set_attr "type" "mmxcvt,sselog1") > (set_attr "length_immediate" "1") > - (set_attr "mode" "DI")]) > + (set_attr "mode" "DI,TI")]) > > (define_expand "mmx_pshufw" > [(match_operand:V4HI 0 "register_operand") > -- > 2.20.1 > >