From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2118 invoked by alias); 3 Oct 2015 08:17:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 2106 invoked by uid 89); 3 Oct 2015 08:17:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-vk0-f50.google.com Received: from mail-vk0-f50.google.com (HELO mail-vk0-f50.google.com) (209.85.213.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Sat, 03 Oct 2015 08:17:00 +0000 Received: by vkgd64 with SMTP id d64so72657575vkg.0 for ; Sat, 03 Oct 2015 01:16:58 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.31.34.7 with SMTP id i7mr11776734vki.60.1443860218499; Sat, 03 Oct 2015 01:16:58 -0700 (PDT) Received: by 10.103.40.68 with HTTP; Sat, 3 Oct 2015 01:16:58 -0700 (PDT) In-Reply-To: <20151002161215.GF5228@msticlxl57.ims.intel.com> References: <20150921141442.GD49423@msticlxl57.ims.intel.com> <20150921142728.GB1847@tucnak.redhat.com> <20150921165719.GA14053@msticlxl57.ims.intel.com> <20150922093120.GA10287@msticlxl57.ims.intel.com> <20151002161215.GF5228@msticlxl57.ims.intel.com> Date: Sat, 03 Oct 2015 08:17:00 -0000 Message-ID: Subject: Re: [PATCH, i386] Introduce switch for Skylake Server CPU. From: Uros Bizjak To: Kirill Yukhin Cc: Jakub Jelinek , GCC Patches Content-Type: text/plain; charset=UTF-8 X-SW-Source: 2015-10/txt/msg00299.txt.bz2 On Fri, Oct 2, 2015 at 6:12 PM, Kirill Yukhin wrote: > Hello, > > Patch in the bottom introduces cpuid detection > for Skylake CPU supporting AVX-512. > > Bootstrapped. Changed test pass. Is it ok for trunk? > > libgcc/ > * libgcc/config/i386/cpuinfo.c (get_intel_cpu): Detect "skylake-avx512". > > gcc/testsuite/ > * gcc.target/i386/builtin_target.c: Add check for "skylake-avx512". OK. Thanks, Uros. > -- > Thanks, K > > commit 230beb0d31a9463c8339975580142298138442f6 > Author: Kirill Yukhin > Date: Fri Oct 2 19:03:21 2015 +0300 > > AVX-512. Add family/model to cpuinfo.c. > > diff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c > index a9a8753..82357a7 100644 > --- a/gcc/testsuite/gcc.target/i386/builtin_target.c > +++ b/gcc/testsuite/gcc.target/i386/builtin_target.c > @@ -91,6 +91,11 @@ check_intel_cpu_model (unsigned int family, unsigned int model, > assert (__builtin_cpu_is ("corei7")); > assert (__builtin_cpu_is ("skylake")); > break; > + case 0x55: > + /* Skylake with AVX-512 support. */ > + assert (__builtin_cpu_is ("corei7")); > + assert (__builtin_cpu_is ("skylake-avx512")); > + break; > case 0x17: > case 0x1d: > /* Penryn. */ > diff --git a/libgcc/config/i386/cpuinfo.c b/libgcc/config/i386/cpuinfo.c > index 40ed84c..0cbbc85 100644 > --- a/libgcc/config/i386/cpuinfo.c > +++ b/libgcc/config/i386/cpuinfo.c > @@ -78,6 +78,7 @@ enum processor_subtypes > INTEL_COREI7_HASWELL, > INTEL_COREI7_BROADWELL, > INTEL_COREI7_SKYLAKE, > + INTEL_COREI7_SKYLAKE_AVX512, > CPU_SUBTYPE_MAX > }; > > @@ -260,6 +261,11 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id) > __cpu_model.__cpu_type = INTEL_COREI7; > __cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE; > break; > + case 0x55: > + /* Skylake with AVX-512 support. */ > + __cpu_model.__cpu_type = INTEL_COREI7; > + __cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512; > + break; > case 0x17: > case 0x1d: > /* Penryn. */