From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by sourceware.org (Postfix) with ESMTPS id 510263857342 for ; Fri, 16 Jun 2023 07:13:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 510263857342 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qk1-x72a.google.com with SMTP id af79cd13be357-75ebd39fac8so48321085a.3 for ; Fri, 16 Jun 2023 00:13:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686899612; x=1689491612; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=3xMmmnSV288f5Twk6pm8H/ev9jEveZf/AkmAPLOOkMk=; b=Ugc/stsNwVoLwjXP4Kom40suzuUxgmauuXqLf2t9aCkdee+JDlhegNWYDW45vEvqnP 6I8DQlcI4FHXlBIvD7jqH2MUEQBkOt/FyPwtD0uCsnFozhezimAlRTXWOg8XF+NzKcDK cbu4MYKPy7ZArejAABxtet6SA0XfX9veilVvdyVG8AXZ6qQ1G1NDtVmFlcLuD11ErqCD RaZP+dNHeT85EvUWGUs8aYyqIMLw4DEREpJfNYp8BMpQME4+pyB7/p4/mWTpA7DIM4Wz LWdYmmA732lyzkGhU0jEubLVtiLl9cPvUVbJ8PoZzux/Th5pCJ8sSDho/V0vnvUMMBaI 1b6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686899612; x=1689491612; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3xMmmnSV288f5Twk6pm8H/ev9jEveZf/AkmAPLOOkMk=; b=F2pdRTk5WDeJFKidWVXKxQ6bVN7uS/iiie0csPbddeEyQcc5e6H8Htrh7kf+ZdscAc s9468XfmeAZWP6lXXfNRT/a6/q32QImskyBbgoR5nWyxDGP4hhfO7zgHBg9PYVj2uxO6 C7VzkMu6msZY7oOlTSbEaEaLIKGrsucZuM398e2JUfh68rPZmuHcmdnC0MndgbOv7QcE v2V2H+jUnwvYT5PAcoOo4aRPKeP9IN4nmFOYALcisszWbxMXRx5X37qmCGLpdJeMMFxU ApoMCNQKw5tLWzpFP7l3JAmESWtj5FNIGFQhWisls+f1ve8fuE7iaIj9qgfoiAVCPvTz eq7A== X-Gm-Message-State: AC+VfDwv0q1S59f8IBan6JPETu6Wd3D65imzfm5rmLODhdra4MH2I/Y+ jqPVFOr6u02Dgl/DFSRy6tQ32TYt3uYXxWCdPtBMuW2Tv7s= X-Google-Smtp-Source: ACHHUZ7QqP94oSX/OAHw8keOpXU7U8XzbWPd/eAgJ/wJEKW+Yvkkqb7Ps24+R1e6NNUK6AJqGjcmqq3PG8nxDsts6eo= X-Received: by 2002:a05:6214:2242:b0:624:3af6:21d2 with SMTP id c2-20020a056214224200b006243af621d2mr1516519qvc.13.1686899612356; Fri, 16 Jun 2023 00:13:32 -0700 (PDT) MIME-Version: 1.0 References: <037101d998cb$6aa8f120$3ffad360$@nextmovesoftware.com> <006701d99fd5$63e988c0$2bbc9a40$@nextmovesoftware.com> In-Reply-To: <006701d99fd5$63e988c0$2bbc9a40$@nextmovesoftware.com> From: Uros Bizjak Date: Fri, 16 Jun 2023 09:13:26 +0200 Message-ID: Subject: Re: [x86 PATCH] PR target/31985: Improve memory operand use with doubleword add. To: Roger Sayle Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, Jun 16, 2023 at 12:04=E2=80=AFAM Roger Sayle wrote: > > > Hi Uros, > > > On the 7th June 2023, Uros Bizkak wrote: > > The register allocator considers the instruction-to-be-split as one ins= truction, so it > > can allocate output register to match an input register (or a register = that forms an > > input address), So, you have to either add an early clobber to the outp= ut, or > > somehow prevent output to clobber registers in the second pattern. > > This implements your suggestion of adding an early clobber to the output,= a > one character ('&') change from the previous version of this patch. Rete= sted > with make bootstrap and make -k check, with and without -m32, to confirm > there are no issues, and this still fixes the pr31985.c test case. > > As you've suggested, I'm also working on improving STV in this area. > > Ok for mainline? > > > 2023-06-15 Roger Sayle > Uros Bizjak > > gcc/ChangeLog > PR target/31985 > * config/i386/i386.md (*add3_doubleword_concat): New > define_insn_and_split combine *add3_doubleword with a > *concat3 for more efficient lowering after reload. > > gcc/testsuite/ChangeLog > PR target/31985 > * gcc.target/i386/pr31985.c: New test case. OK with a small change below. Thanks, Uros. +(define_insn_and_split "*add3_doubleword_concat" + [(set (match_operand: 0 "register_operand" "=3D&r") + (plus: + (any_or_plus: + (ashift: + (zero_extend: + (match_operand:DWIH 2 "nonimmediate_operand" "rm")) + (match_operand: 3 "const_int_operand")) The above mode should be QImode, all shifts have QImode on x86. + (zero_extend: + (match_operand:DWIH 4 "nonimmediate_operand" "rm"))) + (match_operand: 1 "register_operand" "0"))) + (clobber (reg:CC FLAGS_REG))] + "INTVAL (operands[3]) =3D=3D * BITS_PER_UNIT" + "#" + "&& reload_completed" + [(parallel [(set (reg:CCC FLAGS_REG) + (compare:CCC + (plus:DWIH (match_dup 1) (match_dup 4)) + (match_dup 1))) + (set (match_dup 0) + (plus:DWIH (match_dup 1) (match_dup 4)))]) + (parallel [(set (match_dup 5) + (plus:DWIH + (plus:DWIH + (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0)) + (match_dup 6)) + (match_dup 2))) + (clobber (reg:CC FLAGS_REG))])] + "split_double_mode (mode, &operands[0], 2, &operands[0], &operands[5= ]);") + > Roger > -- >