diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index fee4d07b7fd..4dfe7d6c282 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -4204,16 +4204,32 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1, else if (code == GT && TARGET_SSE4_1) gen = gen_sminv16qi3; break; + case E_V8QImode: + if (code == GTU && TARGET_SSE2) + gen = gen_uminv8qi3; + else if (code == GT && TARGET_SSE4_1) + gen = gen_sminv8qi3; + break; case E_V8HImode: if (code == GTU && TARGET_SSE4_1) gen = gen_uminv8hi3; else if (code == GT && TARGET_SSE2) gen = gen_sminv8hi3; break; + case E_V4HImode: + if (code == GTU && TARGET_SSE4_1) + gen = gen_uminv4hi3; + else if (code == GT && TARGET_SSE2) + gen = gen_sminv4hi3; + break; case E_V4SImode: if (TARGET_SSE4_1) gen = (code == GTU) ? gen_uminv4si3 : gen_sminv4si3; break; + case E_V2SImode: + if (TARGET_SSE4_1) + gen = (code == GTU) ? gen_uminv2si3 : gen_sminv2si3; + break; case E_V2DImode: if (TARGET_AVX512VL) { @@ -4254,6 +4270,7 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1, case E_V8SImode: case E_V4DImode: case E_V4SImode: + case E_V2SImode: case E_V2DImode: { rtx t1, t2, mask; @@ -4278,7 +4295,9 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1, case E_V32QImode: case E_V16HImode: case E_V16QImode: + case E_V8QImode: case E_V8HImode: + case E_V4HImode: /* Perform a parallel unsigned saturating subtraction. */ x = gen_reg_rtx (mode); emit_insn (gen_rtx_SET diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 780da108a7c..06b0f5814ea 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -15284,6 +15284,7 @@ ix86_build_const_vector (machine_mode mode, bool vect, rtx value) case E_V16SImode: case E_V8SImode: case E_V4SImode: + case E_V2SImode: case E_V8DImode: case E_V4DImode: case E_V2DImode: @@ -15334,6 +15335,7 @@ ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert) case E_V8SFmode: case E_V4SFmode: case E_V2SFmode: + case E_V2SImode: vec_mode = mode; imode = SImode; break; diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 4c2b724dc6f..347295afbb5 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -52,6 +52,7 @@ (define_mode_iterator MMXMODE [V8QI V4HI V2SI V1DI V2SF]) ;; Mix-n-match (define_mode_iterator MMXMODE12 [V8QI V4HI]) +(define_mode_iterator MMXMODE14 [V8QI V2SI]) (define_mode_iterator MMXMODE24 [V4HI V2SI]) (define_mode_iterator MMXMODE248 [V4HI V2SI V1DI]) @@ -1417,6 +1418,31 @@ (define_insn "*sse2_umulv1siv1di3" (set_attr "type" "mmxmul,ssemul,ssemul") (set_attr "mode" "DI,TI,TI")]) +(define_expand "3" + [(set (match_operand:MMXMODE14 0 "register_operand") + (smaxmin:MMXMODE14 + (match_operand:MMXMODE14 1 "register_operand") + (match_operand:MMXMODE14 2 "register_operand")))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_insn "*mmx_3" + [(set (match_operand:MMXMODE14 0 "register_operand" "=Yr,*x,Yv") + (smaxmin:MMXMODE14 + (match_operand:MMXMODE14 1 "register_operand" "%0,0,Yv") + (match_operand:MMXMODE14 2 "register_operand" "Yr,*x,Yv")))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1 + && ix86_binary_operator_ok (, mode, operands)" + "@ + p\t{%2, %0|%0, %2} + p\t{%2, %0|%0, %2} + vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "sseiadd") + (set_attr "prefix_extra" "1,1,*") + (set_attr "prefix" "orig,orig,vex") + (set_attr "mode" "TI")]) + (define_expand "mmx_v4hi3" [(set (match_operand:V4HI 0 "register_operand") (smaxmin:V4HI @@ -1451,6 +1477,31 @@ (define_insn "*mmx_v4hi3" (set_attr "type" "mmxadd,sseiadd,sseiadd") (set_attr "mode" "DI,TI,TI")]) +(define_expand "3" + [(set (match_operand:MMXMODE24 0 "register_operand") + (umaxmin:MMXMODE24 + (match_operand:MMXMODE24 1 "register_operand") + (match_operand:MMXMODE24 2 "register_operand")))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_insn "*mmx_3" + [(set (match_operand:MMXMODE24 0 "register_operand" "=Yr,*x,Yv") + (umaxmin:MMXMODE24 + (match_operand:MMXMODE24 1 "register_operand" "%0,0,Yv") + (match_operand:MMXMODE24 2 "register_operand" "Yr,*x,Yv")))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1 + && ix86_binary_operator_ok (, mode, operands)" + "@ + p\t{%2, %0|%0, %2} + p\t{%2, %0|%0, %2} + vp\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "sseiadd") + (set_attr "prefix_extra" "1,1,*") + (set_attr "prefix" "orig,orig,vex") + (set_attr "mode" "TI")]) + (define_expand "mmx_v8qi3" [(set (match_operand:V8QI 0 "register_operand") (umaxmin:V8QI @@ -1582,6 +1633,73 @@ (define_insn "mmx_gt3" (set_attr "type" "mmxcmp,ssecmp,ssecmp") (set_attr "mode" "DI,TI,TI")]) +(define_expand "vec_cmp" + [(set (match_operand:MMXMODEI 0 "register_operand") + (match_operator:MMXMODEI 1 "" + [(match_operand:MMXMODEI 2 "register_operand") + (match_operand:MMXMODEI 3 "register_operand")]))] + "TARGET_MMX_WITH_SSE" +{ + bool ok = ix86_expand_int_vec_cmp (operands); + gcc_assert (ok); + DONE; +}) + +(define_expand "vec_cmpu" + [(set (match_operand:MMXMODEI 0 "register_operand") + (match_operator:MMXMODEI 1 "" + [(match_operand:MMXMODEI 2 "register_operand") + (match_operand:MMXMODEI 3 "register_operand")]))] + "TARGET_MMX_WITH_SSE" +{ + bool ok = ix86_expand_int_vec_cmp (operands); + gcc_assert (ok); + DONE; +}) + +(define_expand "vcond" + [(set (match_operand:MMXMODEI 0 "register_operand") + (if_then_else:MMXMODEI + (match_operator 3 "" + [(match_operand:MMXMODEI 4 "register_operand") + (match_operand:MMXMODEI 5 "register_operand")]) + (match_operand:MMXMODEI 1) + (match_operand:MMXMODEI 2)))] + "TARGET_MMX_WITH_SSE" +{ + bool ok = ix86_expand_int_vcond (operands); + gcc_assert (ok); + DONE; +}) + +(define_expand "vcondu" + [(set (match_operand:MMXMODEI 0 "register_operand") + (if_then_else:MMXMODEI + (match_operator 3 "" + [(match_operand:MMXMODEI 4 "register_operand") + (match_operand:MMXMODEI 5 "register_operand")]) + (match_operand:MMXMODEI 1) + (match_operand:MMXMODEI 2)))] + "TARGET_MMX_WITH_SSE" +{ + bool ok = ix86_expand_int_vcond (operands); + gcc_assert (ok); + DONE; +}) + +(define_expand "vcond_mask_" + [(set (match_operand:MMXMODEI 0 "register_operand") + (vec_merge:MMXMODEI + (match_operand:MMXMODEI 1 "register_operand") + (match_operand:MMXMODEI 2 "register_operand") + (match_operand:MMXMODEI 3 "register_operand")))] + "TARGET_MMX_WITH_SSE" +{ + ix86_expand_sse_movcc (operands[0], operands[3], + operands[1], operands[2]); + DONE; +}) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral logical operations diff --git a/gcc/testsuite/gcc.dg/vect/vect-bool-cmp.c b/gcc/testsuite/gcc.dg/vect/vect-bool-cmp.c index 35d2a3ca02e..c97da528914 100644 --- a/gcc/testsuite/gcc.dg/vect/vect-bool-cmp.c +++ b/gcc/testsuite/gcc.dg/vect/vect-bool-cmp.c @@ -253,4 +253,4 @@ main (int argc, char **argv) check (res, ne); } -/* { dg-final { scan-tree-dump-times "VECTORIZED" 18 "vect" { target sse4_runtime } } } */ +/* { dg-final { scan-tree-dump-times "LOOP VECTORIZED" 18 "vect" { target sse4_runtime } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr98218-1.c b/gcc/testsuite/gcc.target/i386/pr98218-1.c new file mode 100644 index 00000000000..48407dabc2a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98218-1.c @@ -0,0 +1,21 @@ +/* PR target/98522 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2" } */ + +typedef char vec __attribute__((vector_size(8))); + +vec lt (vec a, vec b) { return a < b; } +vec le (vec a, vec b) { return a <= b; } +vec eq (vec a, vec b) { return a == b; } +vec ne (vec a, vec b) { return a != b; } +vec ge (vec a, vec b) { return a >= b; } +vec gt (vec a, vec b) { return a > b; } + +typedef unsigned char uvec __attribute__((vector_size(8))); + +vec ltu (uvec a, uvec b) { return a < b; } +vec leu (uvec a, uvec b) { return a <= b; } +vec geu (uvec a, uvec b) { return a >= b; } +vec gtu (uvec a, uvec b) { return a > b; } + +/* { dg-final { scan-assembler-not "cmpb" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr98218-1a.c b/gcc/testsuite/gcc.target/i386/pr98218-1a.c new file mode 100644 index 00000000000..3470c87cdc3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98218-1a.c @@ -0,0 +1,19 @@ +/* PR target/98522 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ + +typedef char T; + +#define M 8 + +extern T a[M], b[M], s1[M], s2[M], r[M]; + +void foo (void) +{ + int j; + + for (j = 0; j < M; j++) + r[j] = (a[j] < b[j]) ? s1[j] : s2[j]; +} + +/* { dg-final { scan-assembler "pcmpgtb" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr98218-2.c b/gcc/testsuite/gcc.target/i386/pr98218-2.c new file mode 100644 index 00000000000..0b716126413 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98218-2.c @@ -0,0 +1,21 @@ +/* PR target/98522 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2" } */ + +typedef short vec __attribute__((vector_size(8))); + +vec lt (vec a, vec b) { return a < b; } +vec le (vec a, vec b) { return a <= b; } +vec eq (vec a, vec b) { return a == b; } +vec ne (vec a, vec b) { return a != b; } +vec ge (vec a, vec b) { return a >= b; } +vec gt (vec a, vec b) { return a > b; } + +typedef unsigned short uvec __attribute__((vector_size(8))); + +vec ltu (uvec a, uvec b) { return a < b; } +vec leu (uvec a, uvec b) { return a <= b; } +vec geu (uvec a, uvec b) { return a >= b; } +vec gtu (uvec a, uvec b) { return a > b; } + +/* { dg-final { scan-assembler-not "cmpw" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr98218-2a.c b/gcc/testsuite/gcc.target/i386/pr98218-2a.c new file mode 100644 index 00000000000..6afd0a412d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98218-2a.c @@ -0,0 +1,19 @@ +/* PR target/98522 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ + +typedef short T; + +#define M 4 + +extern T a[M], b[M], s1[M], s2[M], r[M]; + +void foo (void) +{ + int j; + + for (j = 0; j < M; j++) + r[j] = (a[j] < b[j]) ? s1[j] : s2[j]; +} + +/* { dg-final { scan-assembler "pcmpgtw" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr98218-3.c b/gcc/testsuite/gcc.target/i386/pr98218-3.c new file mode 100644 index 00000000000..83a8c298640 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98218-3.c @@ -0,0 +1,21 @@ +/* PR target/98522 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2" } */ + +typedef int vec __attribute__((vector_size(8))); + +vec lt (vec a, vec b) { return a < b; } +vec le (vec a, vec b) { return a <= b; } +vec eq (vec a, vec b) { return a == b; } +vec ne (vec a, vec b) { return a != b; } +vec ge (vec a, vec b) { return a >= b; } +vec gt (vec a, vec b) { return a > b; } + +typedef unsigned int uvec __attribute__((vector_size(8))); + +vec ltu (uvec a, uvec b) { return a < b; } +vec leu (uvec a, uvec b) { return a <= b; } +vec geu (uvec a, uvec b) { return a >= b; } +vec gtu (uvec a, uvec b) { return a > b; } + +/* { dg-final { scan-assembler-not "cmpl" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr98218-3a.c b/gcc/testsuite/gcc.target/i386/pr98218-3a.c new file mode 100644 index 00000000000..272d54e5b34 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98218-3a.c @@ -0,0 +1,19 @@ +/* PR target/98522 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -ftree-vectorize -msse2" } */ + +typedef int T; + +#define M 2 + +extern T a[M], b[M], s1[M], s2[M], r[M]; + +void foo (void) +{ + int j; + + for (j = 0; j < M; j++) + r[j] = (a[j] < b[j]) ? s1[j] : s2[j]; +} + +/* { dg-final { scan-assembler "pcmpgtd" { xfail *-*-* } } } */