* [PATCH, i386]: Fix PR79495, ICE in extract_constrain_insn with -msoft-float
@ 2017-02-14 17:48 Uros Bizjak
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From: Uros Bizjak @ 2017-02-14 17:48 UTC (permalink / raw)
To: gcc-patches
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Attached patch adds correct alternative fo 64-bit targets. On these
targets, we have to prevent alternatives that split to moves from
DImode immediates outside signed 32-bit range to a memory.
2017-02-14 Uros Bizjak <ubizjak@gmail.com>
PR target/79495
* config/i386/i386.md (*movxf_internal): Add (o,rC) alternative.
testsuite/ChangeLog:
2017-02-14 Uros Bizjak <ubizjak@gmail.com>
PR target/79495
* gcc.target/i386/pr79495.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline, will be backported to gcc-6 branch.
Uros.
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Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 245433)
+++ config/i386/i386.md (working copy)
@@ -3248,9 +3248,9 @@
;; in alternatives 4, 6, 7 and 8.
(define_insn "*movxf_internal"
[(set (match_operand:XF 0 "nonimmediate_operand"
- "=f,m,f,?r ,!o,?*r ,!o,!o,!o,r ,o")
+ "=f,m,f,?r ,!o,?*r ,!o,!o,!o,r ,o ,o")
(match_operand:XF 1 "general_operand"
- "fm,f,G,roF,r , *roF,*r,F ,C,roF,rF"))]
+ "fm,f,G,roF,r ,*roF,*r,F ,C ,roF,rF,rC"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (lra_in_progress || reload_completed
|| !CONST_DOUBLE_P (operands[1])
@@ -3277,19 +3277,19 @@
}
}
[(set (attr "isa")
- (cond [(eq_attr "alternative" "7")
+ (cond [(eq_attr "alternative" "7,10")
(const_string "nox64")
- (eq_attr "alternative" "8")
+ (eq_attr "alternative" "8,11")
(const_string "x64")
]
(const_string "*")))
(set (attr "type")
- (cond [(eq_attr "alternative" "3,4,5,6,7,8,9,10")
+ (cond [(eq_attr "alternative" "3,4,5,6,7,8,9,10,11")
(const_string "multi")
]
(const_string "fmov")))
(set (attr "mode")
- (cond [(eq_attr "alternative" "3,4,5,6,7,8,9,10")
+ (cond [(eq_attr "alternative" "3,4,5,6,7,8,9,10,11")
(if_then_else (match_test "TARGET_64BIT")
(const_string "DI")
(const_string "SI"))
@@ -3300,7 +3300,7 @@
(symbol_ref "false")]
(symbol_ref "true")))
(set (attr "enabled")
- (cond [(eq_attr "alternative" "9,10")
+ (cond [(eq_attr "alternative" "9,10,11")
(if_then_else
(match_test "TARGET_HARD_XF_REGS")
(symbol_ref "false")
Index: testsuite/gcc.target/i386/pr79495.c
===================================================================
--- testsuite/gcc.target/i386/pr79495.c (nonexistent)
+++ testsuite/gcc.target/i386/pr79495.c (working copy)
@@ -0,0 +1,11 @@
+/* PR target/79495 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -msoft-float" } */
+
+long double dnan = 1.0l/0.0l - 1.0l/0.0l;
+long double x = 1.0l;
+void fn1 (void)
+{
+ if (dnan != x)
+ x = 1.0;
+}
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2017-02-14 17:48 [PATCH, i386]: Fix PR79495, ICE in extract_constrain_insn with -msoft-float Uros Bizjak
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