From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by sourceware.org (Postfix) with ESMTPS id 35F0D3858CDB for ; Wed, 24 May 2023 12:26:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 35F0D3858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-qk1-x736.google.com with SMTP id af79cd13be357-75b17aa343dso73141585a.3 for ; Wed, 24 May 2023 05:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1684931161; x=1687523161; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=GGH7eQk9ccLf/xkaWZhRF7qweGm9LnQTZNOaUawhonQ=; b=PwfrV4atVe8V0xRGzc5T+JOxInouSDJXuCfuMf48cx/JPHAu4o4ZIJd0BodWVcg6g+ aoGaKlT+0MmmoiYN5YIia8OmPzfpmbheHyUAEbKQ+AXPhskrmYNWsUFXwFYWcM1OOdZW j8tFkRQokiLeVQeY5H5L6GPxfcNsnkGfDIhH9eXS7mR7mb8g5LPe5HKfAtpM6S+D0qPV 03VWU1lfWuGE19FcOdbNdE++PG8sSP/FjaH1m4kRcJ3OKOAvtsdCzz6xNXhCSCPj9vLV rYVLTzKgAXX/rN3NHsL3pyMBmYZFxCpM0uHbbe7uMMzbFJq5xzSXg0BvaSNb2x/SNM0W 3pmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684931161; x=1687523161; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GGH7eQk9ccLf/xkaWZhRF7qweGm9LnQTZNOaUawhonQ=; b=EWziH/kT1e6vDQ7N7WBavlHAdwVfUOtZALcjqNwAJ8m9QqIQho7D43nB1WFF5FZJnF 4EAvAmiVXTtEXqSL0rupfrYbXcnGmZSXkUET0ZdCQf++/AKNoklUmkzBWBB0ZBsh72ye +yhVhgLISBVorC7lGojkhPSVtRgftDqfPQH4sWXm1AEEWLN7WlPfLgZdkA8k2zTEQ3U0 kEX1RsYQvDP8CGInPHnPhGNNMPIm9XL6WNOvik8OXsTva9p0Ebm1S/YKCOZ4NrKsWLow 0V0/HNpSfu0CsP+8goX2kBxosWxvXokzJQ0lOYqU6w20+/5CGxju0nr/9gt8iC3AFW5U vNSA== X-Gm-Message-State: AC+VfDy2O8kTm0OvKzlL1aAXlEyb03Lvf2ihqYkbhKVa8/DVcEkjR6MR QBRMB4ts725AEuDxorU8VMHVCFxagTuugEx6rEo= X-Google-Smtp-Source: ACHHUZ4eqS9jGz0aeoWZU5aLdvO8MS8Qgw3zkWMvytmKZH37jFHRXGnrhC//XFIojj56hyo+Y/ntZMyrCp6TbJd9Z7Q= X-Received: by 2002:ad4:5d4e:0:b0:5ef:1e0a:1b07 with SMTP id jk14-20020ad45d4e000000b005ef1e0a1b07mr29932260qvb.40.1684931161218; Wed, 24 May 2023 05:26:01 -0700 (PDT) MIME-Version: 1.0 References: <646de365.5d0a0220.695c1.0c25SMTPIN_ADDED_MISSING@mx.google.com> In-Reply-To: <646de365.5d0a0220.695c1.0c25SMTPIN_ADDED_MISSING@mx.google.com> From: Uros Bizjak Date: Wed, 24 May 2023 14:25:49 +0200 Message-ID: Subject: Re: [PATCH] target/109944 - avoid STLF fail for V16QImode CTOR expansion To: Richard Biener Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, May 24, 2023 at 12:13=E2=80=AFPM Richard Biener = wrote: > > The following dispatches to V2DImode CTOR expansion instead of > using sets of (subreg:DI (reg:V16QI 146) [08]) which causes > LRA to spill DImode and reload V16QImode. The same applies for > V8QImode or V4HImode construction from SImode parts which happens > during 32bit libgcc build. > > Boostrapped and tested on x86_64-unknown-linux-gnu. > > OK? > > Thanks, > Richard. > > PR target/109944 > * config/i386/i386-expand.cc (ix86_expand_vector_init_general): > Perform final vector composition using > ix86_expand_vector_init_general instead of setting > the highpart and lowpart which causes spilling. > > * gcc.target/i386/pr109944-1.c: New testcase. > * gcc.target/i386/pr109944-2.c: Likewise. OK. Thanks, Uros. > --- > gcc/config/i386/i386-expand.cc | 11 ++++---- > gcc/testsuite/gcc.target/i386/pr109944-1.c | 30 ++++++++++++++++++++++ > gcc/testsuite/gcc.target/i386/pr109944-2.c | 17 ++++++++++++ > 3 files changed, 53 insertions(+), 5 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr109944-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/pr109944-2.c > > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand= .cc > index ff3d382f1b4..19acd9c01f9 100644 > --- a/gcc/config/i386/i386-expand.cc > +++ b/gcc/config/i386/i386-expand.cc > @@ -16367,11 +16367,12 @@ quarter: > emit_move_insn (target, gen_lowpart (mode, words[0])); > else if (n_words =3D=3D 2) > { > - rtx tmp =3D gen_reg_rtx (mode); > - emit_clobber (tmp); > - emit_move_insn (gen_lowpart (tmp_mode, tmp), words[0]); > - emit_move_insn (gen_highpart (tmp_mode, tmp), words[1]); > - emit_move_insn (target, tmp); > + gcc_assert (tmp_mode =3D=3D DImode || tmp_mode =3D=3D SImode); > + machine_mode concat_mode =3D tmp_mode =3D=3D DImode ? V2DImode = : V2SImode; > + rtx tmp =3D gen_reg_rtx (concat_mode); > + vals =3D gen_rtx_PARALLEL (concat_mode, gen_rtvec_v (2, words))= ; > + ix86_expand_vector_init_general (false, concat_mode, tmp, vals)= ; > + emit_move_insn (target, gen_lowpart (mode, tmp)); > } > else if (n_words =3D=3D 4) > { > diff --git a/gcc/testsuite/gcc.target/i386/pr109944-1.c b/gcc/testsuite/g= cc.target/i386/pr109944-1.c > new file mode 100644 > index 00000000000..d82214d9ebc > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr109944-1.c > @@ -0,0 +1,30 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > + > +void foo (char * __restrict a, char *b) > +{ > + a[0] =3D b[0]; > + a[1] =3D b[16]; > + a[2] =3D b[32]; > + a[3] =3D b[48]; > + a[4] =3D b[64]; > + a[5] =3D b[80]; > + a[6] =3D b[96]; > + a[7] =3D b[112]; > + a[8] =3D b[128]; > + a[9] =3D b[144]; > + a[10] =3D b[160]; > + a[11] =3D b[176]; > + a[12] =3D b[192]; > + a[13] =3D b[208]; > + a[14] =3D b[224]; > + a[15] =3D b[240]; > +} > + > +/* We do not want to generate a spill/reload for when the store is vecto= rized. > + movq %rdx, -24(%rsp) > +... > + movq %rax, -16(%rsp) > + movdqa -24(%rsp), %xmm0 > + movups %xmm0, (%rdi) */ > +/* { dg-final { scan-assembler-not "movdq\[^\r\n\]*\[bs\]p\\\), %xmm" } = } */ > diff --git a/gcc/testsuite/gcc.target/i386/pr109944-2.c b/gcc/testsuite/g= cc.target/i386/pr109944-2.c > new file mode 100644 > index 00000000000..318dfab0250 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr109944-2.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -msse2" } */ > + > +typedef char v16qi __attribute__((vector_size(16))); > +v16qi foo (char *b) > +{ > + return (v16qi){ b[0], b[16], b[32], b[48], b[64], b[80], b[96], b[112]= , > + b[128], b[144], b[160], b[176], b[192], b[208], b[224], b[240] }; > +} > + > +/* We do not want to generate a spill/reload > + movq %rdx, -24(%rsp) > +... > + movq %rax, -16(%rsp) > + movdqa -24(%rsp), %xmm0 > + movups %xmm0, (%rdi) */ > +/* { dg-final { scan-assembler-not "movdq\[^\r\n\]*\[bs\]p\\\), %xmm" } = } */ > -- > 2.35.3