From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf33.google.com (mail-qv1-xf33.google.com [IPv6:2607:f8b0:4864:20::f33]) by sourceware.org (Postfix) with ESMTPS id 5E8083858025 for ; Mon, 16 Nov 2020 10:16:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 5E8083858025 Received: by mail-qv1-xf33.google.com with SMTP id u23so1067778qvf.1 for ; Mon, 16 Nov 2020 02:16:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=2T1y1GGhaX1cHNi8kH9Qu5cSWMntVTtyz+/Iv5IkHAs=; b=NvviUdIHAFUM16uRnfArLGgu+NwBwMDD6XExdu+xiPlNajwq+lwYGQpYzQzFrMO5FK 4G+LVlLNmPxxk2cpyK+nvNte9qHNDqNRSaGvcWPO09rsk9eYb7MutvlZFniVahAVERIf lfRqP1imaToToceYkLKA2uti+ods4KoFf7rq7tHPAeeIoiUZHrzshbw52VeQXzZ0+MUV wL4JAocihXfg9cBUPa+JgrAvt/CLVKgby0ekJEuyBOCIlAWmlbelyPrv0UU+4LHcrdO4 W1g2NQJqSIXQD6PH9SvL7nUCRnC+Vk/abjBmxJpeWATiN0LxQ5rfLV1EUhFFTA7U07Zp XmZA== X-Gm-Message-State: AOAM530XBu4/YoCVtCg4RKEpKd6COVMUrv4CNtXceFDJgxQ5aWfcDPSr OFP1xelZAlMz8mBt/6P6SefhTlOKLEn5dOAz9SU= X-Google-Smtp-Source: ABdhPJw1JvPyapEXKS8Fogl3IwvgCU2zaFgYToW2GHNJnWxj84ylcrFTLdZNNzx3ykxu3iLx6jLojjbXHogBPhsAgbM= X-Received: by 2002:a05:6214:a8f:: with SMTP id ev15mr14627076qvb.20.1605521811913; Mon, 16 Nov 2020 02:16:51 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Uros Bizjak Date: Mon, 16 Nov 2020 11:16:40 +0100 Message-ID: Subject: Re: [PATCH] [PR target/97194] [AVX2] Support variable index vec_set. To: Hongtao Liu Cc: "gcc-patches@gcc.gnu.org" , Richard Biener Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Nov 2020 10:16:53 -0000 On Thu, Nov 12, 2020 at 10:10 AM Hongtao Liu wrote: > > On Thu, Nov 12, 2020 at 4:21 PM Uros Bizjak wrote: > > > > On Thu, Nov 12, 2020 at 3:04 AM Hongtao Liu wrote: > > > > > > > gcc/ChangeLog: > > > > > > > > > > PR target/97194 > > > > > * config/i386/i386-expand.c (ix86_expand_vector_set_var): New function. > > > > > * config/i386/i386-protos.h (ix86_expand_vector_set_var): New Decl. > > > > > * config/i386/predicates.md (vec_setm_operand): New predicate, > > > > > true for const_int_operand or register_operand under TARGET_AVX2. > > > > > * config/i386/sse.md (vec_set): Support both constant > > > > > and variable index vec_set. > > > > > > > > > > gcc/testsuite/ChangeLog: > > > > > > > > > > * gcc.target/i386/avx2-vec-set-1.c: New test. > > > > > * gcc.target/i386/avx2-vec-set-2.c: New test. > > > > > * gcc.target/i386/avx512bw-vec-set-1.c: New test. > > > > > * gcc.target/i386/avx512bw-vec-set-2.c: New test. > > > > > * gcc.target/i386/avx512f-vec-set-2.c: New test. > > > > > * gcc.target/i386/avx512vl-vec-set-2.c: New test. > > > > > > > > +;; True for registers, or const_int_operand, used to vec_setm expander. > > > > +(define_predicate "vec_setm_operand" > > > > + (ior (and (match_operand 0 "register_operand") > > > > + (match_test "TARGET_AVX2")) > > > > + (match_code "const_int"))) > > > > + > > > > ;; True for registers, or 1 or -1. Used to optimize double-word shifts. > > > > (define_predicate "reg_or_pm1_operand" > > > > (ior (match_operand 0 "register_operand") > > > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > > > > index b153a87fb98..1798e5dea75 100644 > > > > --- a/gcc/config/i386/sse.md > > > > +++ b/gcc/config/i386/sse.md > > > > @@ -8098,11 +8098,14 @@ (define_insn "vec_setv2df_0" > > > > (define_expand "vec_set" > > > > [(match_operand:V 0 "register_operand") > > > > (match_operand: 1 "register_operand") > > > > - (match_operand 2 "const_int_operand")] > > > > + (match_operand 2 "vec_setm_operand")] > > > > > > > > You need to specify a mode, otherwise a register of any mode can pass here. > > > > > > > Yes, theoretically, we only accept integer types. But in can_vec_set_var_idx_p > > > cut > > > --- > > > bool > > > can_vec_set_var_idx_p (machine_mode vec_mode) > > > { > > > if (!VECTOR_MODE_P (vec_mode)) > > > return false; > > > > > > machine_mode inner_mode = GET_MODE_INNER (vec_mode); > > > rtx reg1 = alloca_raw_REG (vec_mode, LAST_VIRTUAL_REGISTER + 1); > > > rtx reg2 = alloca_raw_REG (inner_mode, LAST_VIRTUAL_REGISTER + 2); > > > rtx reg3 = alloca_raw_REG (VOIDmode, LAST_VIRTUAL_REGISTER + 3); > > > > > > enum insn_code icode = optab_handler (vec_set_optab, vec_mode); > > > > > > return icode != CODE_FOR_nothing && insn_operand_matches (icode, 0, reg1) > > > && insn_operand_matches (icode, 1, reg2) > > > && insn_operand_matches (icode, 2, reg3); > > > } > > > --- > > > > > > reg3 is assumed to be VOIDmode, set anymode in match_operand 2 will > > > fail insn_operand_matches (icode, 2, reg3) > > > --- > > > (gdb) p insn_operand_matches(icode,2,reg3) > > > $5 = false > > > (gdb) > > > --- > > > > > > Maybe we need to change > > > > > > rtx reg3 = alloca_raw_REG (VOIDmode, LAST_VIRTUAL_REGISTER + 3); > > > > > > to > > > > > > rtx reg3 = alloca_raw_REG (SImode, LAST_VIRTUAL_REGISTER + 3); > > > > > > cc Richard Biener, any thoughts? > > > > There are two targets (gcn in gcn-valu.md and s390 in vector.md) that > > specify SImode for operand 2 in vec_setM pattern and allow register > > operands. I wonder if and how they manage to generate the pattern. > > > > Uros. > > Variable index vec_set is enabled by r11-3486, about two months ago in > [1]. But for the upper two targets, the codes are already there since > GCC10(maybe earlier, i just looked at gcc10 branch), I don't think > those codes are for [1]. OK, let's proceed with the modeless operand. The patch is OK for mainline. Thanks, Uros.