From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by sourceware.org (Postfix) with ESMTPS id E8B6C3858D28 for ; Mon, 17 Jul 2023 11:38:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E8B6C3858D28 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-52164adea19so4286241a12.1 for ; Mon, 17 Jul 2023 04:38:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1689593925; x=1692185925; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Yg/WsagDRT58pRCkOGYQxNB86rX1NyiJEkZ8hrqin6I=; b=fhPPRfiYRoGE7PO49gzyYc1aYWIVrED9sHklBBH6pMdfvKZXg2xv6Ut38g+eC13FqV 5CGoYwKzqxiCDqKH/5ZhS//pskbQHTKRtTd8FwmtfBDAZzjguYkzE/Ss0T2aMiY4Xago Crl6Jhn1WPwdFWYPifOqqr+q/tzOk53GXbA+s5RYDxatou36INcfj87MMU2iDtd4sY1a axlNRxpKZjlwHB2hNVB5yahcocTqMZKXt6zk6adloSUdS8qXQLGC6XNJVUbCJh30KimG g0Fz2035Ymy+sgtGuEDpsVnmaWedsKyIC2IwdcQjojydSQO23dE12zbbH3kqByU1Fo7A 592A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689593925; x=1692185925; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Yg/WsagDRT58pRCkOGYQxNB86rX1NyiJEkZ8hrqin6I=; b=jNCrhEqCuXDlos3wkuwDbsw2kcjTtQUL7pQ37bCyBAIf8leE0UIgseDRb7UaJ32d1H uhRhcBMIYcQWLKUYGeugxP8Q3sWIqYYuVnSdGMf22v5dZlv4ZBaGu22HU/FNnpkuyHxF vzsnPnawU0wOtLAVjl7QcQ9HsO4+ul+WHuPSSWdQxtaswYn1vGVt5J/wknxi1ZFYTw7n 1bYvDhIQWpxs+hWUMRpz4NKETy9MJkLfYbyFOND/L7Gbhb6Jrh78sgKdQCDZEudZWAzv jTNp0yhhxsMUB1UWZsNgXSj75Hn3YMFB9S51M4IUQRZFD06MgQTsLDhX0T5FngoXPbXg xzxQ== X-Gm-Message-State: ABy/qLaywfQp7erb+T3cPQIcV1XMmRJwME3ViftNqGqokFEihur+IDXu aVMDKLRgIOmwRBJCy0nZL+UQRpHwd6gZHtixdTyDfNT0aUk= X-Google-Smtp-Source: APBJJlEWLkt48JnQso4n1UfasyQorCV5t0mJO0gha+sPLJppdZvsb8B7tq4a7mbIXg81Csg9nL5r7OrAtwwphZG5vYc= X-Received: by 2002:a05:6402:1b0e:b0:51e:16ae:b6d7 with SMTP id by14-20020a0564021b0e00b0051e16aeb6d7mr11991826edb.33.1689593924328; Mon, 17 Jul 2023 04:38:44 -0700 (PDT) MIME-Version: 1.0 References: <20230421135347.2519452-1-hongtao.liu@intel.com> In-Reply-To: From: Uros Bizjak Date: Mon, 17 Jul 2023 13:38:33 +0200 Message-ID: Subject: Re: [PATCH 1/2] [i386] Support type _Float16/__bf16 independent of SSE2. To: Hongtao Liu Cc: liuhongt , gcc-patches@gcc.gnu.org, hjl.tools@gmail.com, jakub@redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Jul 17, 2023 at 10:28=E2=80=AFAM Hongtao Liu w= rote: > > I'd like to ping for this patch (only patch 1/2, for patch 2/2, I > think that may not be necessary). > > On Mon, May 15, 2023 at 9:20=E2=80=AFAM Hongtao Liu = wrote: > > > > ping. > > > > On Fri, Apr 21, 2023 at 9:55=E2=80=AFPM liuhongt wrote: > > > > > > > > + if (!TARGET_SSE2) > > > > > + { > > > > > + if (c_dialect_cxx () > > > > > + && cxx_dialect > cxx20) > > > > > > > > Formatting, both conditions are short, so just put them on one line= . > > > Changed. > > > > > > > But for the C++23 macros, more importantly I think we really should > > > > also in ix86_target_macros_internal add > > > > if (c_dialect_cxx () > > > > && cxx_dialect > cxx20 > > > > && (isa_flag & OPTION_MASK_ISA_SSE2)) > > > > { > > > > def_or_undef (parse_in, "__STDCPP_FLOAT16_T__"); > > > > def_or_undef (parse_in, "__STDCPP_BFLOAT16_T__"); > > > > } > > > > plus associated libstdc++ changes. It can be done incrementally th= ough. > > > Added in PATCH 2/2 > > > > > > > > + if (flag_building_libgcc) > > > > > + { > > > > > + /* libbid uses __LIBGCC_HAS_HF_MODE__ and __LIBGCC_HAS_BF= _MODE__ > > > > > + to check backend support of _Float16 and __bf16 type. = */ > > > > > > > > That is actually the case only for HFmode, but not for BFmode right= now. > > > > So, we need further work. One is to add the BFmode support in ther= e, > > > > and another one is make sure the _Float16 <-> _Decimal* and __bf16 = <-> > > > > _Decimal* conversions are compiled in also if not -msse2 by default= . > > > > One way to do that is wrap the HF and BF mode related functions on = x86 > > > > #ifndef __SSE2__ into the pragmas like intrin headers use (but then > > > > perhaps we don't need to undef this stuff here), another is not pro= vide > > > > the hf/bf support in that case from the TUs where they are provided= now, > > > > but from a different one which would be compiled with -msse2. > > > Add CFLAGS-_hf_to_sd.c +=3D -msse2, similar for other files in libbid= , just like > > > we did before for HFtype softfp. Then no need to undef libgcc macros. > > > > > > > > /* We allowed the user to turn off SSE for kernel mode. Don't= crash if > > > > > some less clueful developer tries to use floating-point any= way. */ > > > > > - if (needed_sseregs && !TARGET_SSE) > > > > > + if (needed_sseregs > > > > > + && (!TARGET_SSE > > > > > + || (VALID_SSE2_TYPE_MODE (mode) > > > > > + && !TARGET_SSE2))) > > > > > > > > Formatting, no need to split this up that much. > > > > if (needed_sseregs > > > > && (!TARGET_SSE > > > > || (VALID_SSE2_TYPE_MODE (mode) && !TARGET_SSE2))) > > > > or even better > > > > if (needed_sseregs > > > > && (!TARGET_SSE || (VALID_SSE2_TYPE_MODE (mode) && !TARGET_SS= E2))) > > > > will do it. > > > Changed. > > > > > > > Instead of this, just use > > > > if (!float16_type_node) > > > > { > > > > float16_type_node =3D ix86_float16_type_node; > > > > callback (float16_type_node); > > > > float16_type_node =3D NULL_TREE; > > > > } > > > > if (!bfloat16_type_node) > > > > { > > > > bfloat16_type_node =3D ix86_bf16_type_node; > > > > callback (bfloat16_type_node); > > > > bfloat16_type_node =3D NULL_TREE; > > > > } > > > Changed. > > > > > > > > > > > +static const char * > > > > > +ix86_invalid_conversion (const_tree fromtype, const_tree totype) > > > > > +{ > > > > > + if (element_mode (fromtype) !=3D element_mode (totype)) > > > > > + { > > > > > + /* Do no allow conversions to/from BFmode/HFmode scalar ty= pes > > > > > + when TARGET_SSE2 is not available. */ > > > > > + if ((TYPE_MODE (fromtype) =3D=3D BFmode > > > > > + || TYPE_MODE (fromtype) =3D=3D HFmode) > > > > > + && !TARGET_SSE2) > > > > > > > > First of all, not really sure if this should be purely about scalar > > > > modes, not also complex and vector modes involving those inner mode= s. > > > > Because complex or vector modes with BF/HF elements will be without > > > > TARGET_SSE2 for sure lowered into scalar code and that can't be han= dled > > > > either. > > > > So if (!TARGET_SSE2 && GET_MODE_INNER (TYPE_MODE (fromtype)) =3D=3D= BFmode) > > > > or even better > > > > if (!TARGET_SSE2 && element_mode (fromtype) =3D=3D BFmode) > > > > ? > > > > Or even better remember the 2 modes above into machine_mode tempora= ries > > > > and just use those in the !=3D comparison and for the checks? > > > > > > > > Also, I think it is weird to tell user %<__bf16%> or %<_Float16%> w= hen > > > > we know which one it is. Just return separate messages? > > > Changed. > > > > > > > > + /* Reject all single-operand operations on BFmode/HFmode excep= t for & > > > > > + when TARGET_SSE2 is not available. */ > > > > > + if ((element_mode (type) =3D=3D BFmode || element_mode (type) = =3D=3D HFmode) > > > > > + && !TARGET_SSE2 && op !=3D ADDR_EXPR) > > > > > + return N_("operation not permitted on type %<__bf16%> " > > > > > + "or %<_Float16%> without option %<-msse2%>"); > > > > > > > > Similarly. Also, check !TARGET_SSE2 first as inexpensive one. > > > Changed. > > > > > > > > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > > > Successfully cross-build i686-linux-gnu. > > > Ok for trunk? > > > > > > Enable _Float16 and __bf16 all the time but issue errors when the > > > types are used in conversion, unary operation, binary operation, > > > parameter passing or value return when TARGET_SSE2 is not available. > > > > > > Also undef macros which are used by libgcc/libstdc++ to check the > > > backend support of the _Float16/__bf16 types when TARGET_SSE2 is not > > > available. > > > > > > gcc/ChangeLog: > > > > > > PR target/109504 > > > * config/i386/i386-builtins.cc > > > (ix86_register_float16_builtin_type): Remove TARGET_SSE2. > > > (ix86_register_bf16_builtin_type): Ditto. > > > * config/i386/i386-c.cc (ix86_target_macros): When TARGET_SSE= 2 > > > isn't available, undef the macros which are used to check the > > > backend support of the _Float16/__bf16 types when building > > > libstdc++ and libgcc. > > > * config/i386/i386.cc (construct_container): Issue errors for > > > HFmode/BFmode when TARGET_SSE2 is not available. > > > (function_value_32): Ditto. > > > (ix86_scalar_mode_supported_p): Remove TARGET_SSE2 for HFmode= /BFmode. > > > (ix86_libgcc_floating_mode_supported_p): Ditto. > > > (ix86_emit_support_tinfos): Adjust codes. > > > (ix86_invalid_conversion): New function. > > > (ix86_invalid_unary_op): Ditto. > > > (ix86_invalid_binary_op): Ditto. > > > (TARGET_INVALID_CONVERSION): Define. > > > (TARGET_INVALID_UNARY_OP): Define. > > > (TARGET_INVALID_BINARY_OP): Define. > > > * config/i386/immintrin.h [__SSE2__]: Remove for fp16/bf16 > > > related instrinsics header files. > > > * config/i386/i386.h (VALID_SSE2_TYPE_MODE): New macro. > > > > > > gcc/testsuite/ChangeLog: > > > > > > * gcc.target/i386/pr109504.c: New test. > > > * gcc.target/i386/sse2-bfloat16-1.c: Adjust error info. > > > * gcc.target/i386/sse2-float16-1.c: Ditto. > > > * gcc.target/i386/sse2-float16-4.c: New test. > > > * gcc.target/i386/sse2-float16-5.c: New test. > > > * g++.target/i386/float16-1.C: Adjust error info. > > > > > > libgcc/ChangeLog: > > > > > > * config/i386/t-softfp: Add -msse2 to libbid HFtype related > > > files. LGTM, if you need someone to rubber-stamp the patch. I'm not really versed in this part of the compiler, so please wait a day if someone has anything to say about the patch. Thanks, Uros. > > > --- > > > gcc/config/i386/i386-builtins.cc | 4 +- > > > gcc/config/i386/i386-c.cc | 15 ++ > > > gcc/config/i386/i386.cc | 130 ++++++++++++++++= -- > > > gcc/config/i386/i386.h | 4 + > > > gcc/config/i386/immintrin.h | 4 - > > > gcc/testsuite/g++.target/i386/float16-1.C | 8 +- > > > gcc/testsuite/gcc.target/i386/pr109504.c | 6 + > > > .../gcc.target/i386/sse2-bfloat16-1.c | 8 +- > > > .../gcc.target/i386/sse2-float16-1.c | 8 +- > > > .../gcc.target/i386/sse2-float16-4.c | 25 ++++ > > > .../gcc.target/i386/sse2-float16-5.c | 24 ++++ > > > libgcc/config/i386/t-softfp | 7 + > > > 12 files changed, 215 insertions(+), 28 deletions(-) > > > create mode 100644 gcc/testsuite/gcc.target/i386/pr109504.c > > > create mode 100644 gcc/testsuite/gcc.target/i386/sse2-float16-4.c > > > create mode 100644 gcc/testsuite/gcc.target/i386/sse2-float16-5.c > > > > > > diff --git a/gcc/config/i386/i386-builtins.cc b/gcc/config/i386/i386-= builtins.cc > > > index fc0c82b156e..1cdabfd3a0a 100644 > > > --- a/gcc/config/i386/i386-builtins.cc > > > +++ b/gcc/config/i386/i386-builtins.cc > > > @@ -1367,7 +1367,7 @@ ix86_register_float16_builtin_type (void) > > > else > > > ix86_float16_type_node =3D float16_type_node; > > > > > > - if (!maybe_get_identifier ("_Float16") && TARGET_SSE2) > > > + if (!maybe_get_identifier ("_Float16")) > > > lang_hooks.types.register_builtin_type (ix86_float16_type_node, > > > "_Float16"); > > > } > > > @@ -1385,7 +1385,7 @@ ix86_register_bf16_builtin_type (void) > > > else > > > ix86_bf16_type_node =3D bfloat16_type_node; > > > > > > - if (!maybe_get_identifier ("__bf16") && TARGET_SSE2) > > > + if (!maybe_get_identifier ("__bf16")) > > > lang_hooks.types.register_builtin_type (ix86_bf16_type_node, "__= bf16"); > > > } > > > > > > diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc > > > index e7bd7cc706c..2f83c9981e1 100644 > > > --- a/gcc/config/i386/i386-c.cc > > > +++ b/gcc/config/i386/i386-c.cc > > > @@ -817,6 +817,21 @@ ix86_target_macros (void) > > > if (!TARGET_80387) > > > cpp_define (parse_in, "_SOFT_FLOAT"); > > > > > > + /* HFmode/BFmode is supported without depending any isa > > > + in scalar_mode_supported_p and libgcc_floating_mode_supported_p= , > > > + but according to psABI, they're really supported w/ SSE2 and ab= ove. > > > + Since libstdc++ uses __STDCPP_FLOAT16_T__ and __STDCPP_BFLOAT16= _T__ > > > + for backend support of the types, undef the macros to avoid > > > + build failure, see PR109504. */ > > > + if (!TARGET_SSE2) > > > + { > > > + if (c_dialect_cxx () && cxx_dialect > cxx20) > > > + { > > > + cpp_undef (parse_in, "__STDCPP_FLOAT16_T__"); > > > + cpp_undef (parse_in, "__STDCPP_BFLOAT16_T__"); > > > + } > > > + } > > > + > > > if (TARGET_LONG_DOUBLE_64) > > > cpp_define (parse_in, "__LONG_DOUBLE_64__"); > > > > > > diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc > > > index fbd33a6bfd1..633a0f41e60 100644 > > > --- a/gcc/config/i386/i386.cc > > > +++ b/gcc/config/i386/i386.cc > > > @@ -2651,7 +2651,8 @@ construct_container (machine_mode mode, machine= _mode orig_mode, > > > > > > /* We allowed the user to turn off SSE for kernel mode. Don't cra= sh if > > > some less clueful developer tries to use floating-point anyway.= */ > > > - if (needed_sseregs && !TARGET_SSE) > > > + if (needed_sseregs > > > + && (!TARGET_SSE || (VALID_SSE2_TYPE_MODE (mode) && !TARGET_SSE= 2))) > > > { > > > /* Return early if we shouldn't raise an error for invalid > > > calls. */ > > > @@ -2661,13 +2662,19 @@ construct_container (machine_mode mode, machi= ne_mode orig_mode, > > > { > > > if (!issued_sse_ret_error) > > > { > > > - error ("SSE register return with SSE disabled"); > > > + if (VALID_SSE2_TYPE_MODE (mode)) > > > + error ("SSE register return with SSE2 disabled"); > > > + else > > > + error ("SSE register return with SSE disabled"); > > > issued_sse_ret_error =3D true; > > > } > > > } > > > else if (!issued_sse_arg_error) > > > { > > > - error ("SSE register argument with SSE disabled"); > > > + if (VALID_SSE2_TYPE_MODE (mode)) > > > + error ("SSE register argument with SSE2 disabled"); > > > + else > > > + error ("SSE register argument with SSE disabled"); > > > issued_sse_arg_error =3D true; > > > } > > > return NULL; > > > @@ -4022,13 +4029,26 @@ function_value_32 (machine_mode orig_mode, ma= chine_mode mode, > > > > > > /* Return __bf16/ _Float16/_Complex _Foat16 by sse register. */ > > > if (mode =3D=3D HFmode || mode =3D=3D BFmode) > > > - regno =3D FIRST_SSE_REG; > > > + { > > > + if (!TARGET_SSE2) > > > + { > > > + error ("SSE register return with SSE2 disabled"); > > > + regno =3D AX_REG; > > > + } > > > + else > > > + regno =3D FIRST_SSE_REG; > > > + } > > > + > > > if (mode =3D=3D HCmode) > > > { > > > + if (!TARGET_SSE2) > > > + error ("SSE register return with SSE2 disabled"); > > > + > > > rtx ret =3D gen_rtx_PARALLEL (mode, rtvec_alloc(1)); > > > XVECEXP (ret, 0, 0) > > > =3D gen_rtx_EXPR_LIST (VOIDmode, > > > - gen_rtx_REG (SImode, FIRST_SSE_REG), > > > + gen_rtx_REG (SImode, > > > + TARGET_SSE2 ? FIRST_SSE_REG= : AX_REG), > > > GEN_INT (0)); > > > return ret; > > > } > > > @@ -22459,7 +22479,7 @@ ix86_scalar_mode_supported_p (scalar_mode mod= e) > > > return default_decimal_float_supported_p (); > > > else if (mode =3D=3D TFmode) > > > return true; > > > - else if ((mode =3D=3D HFmode || mode =3D=3D BFmode) && TARGET_SSE2= ) > > > + else if (mode =3D=3D HFmode || mode =3D=3D BFmode) > > > return true; > > > else > > > return default_scalar_mode_supported_p (mode); > > > @@ -22475,7 +22495,7 @@ ix86_libgcc_floating_mode_supported_p (scalar= _float_mode mode) > > > be defined by the C front-end for AVX512FP16 intrinsics. We wi= ll > > > issue an error in ix86_expand_move for HFmode if AVX512FP16 isn= 't > > > enabled. */ > > > - return (((mode =3D=3D HFmode || mode =3D=3D BFmode) && TARGET_SSE2= ) > > > + return ((mode =3D=3D HFmode || mode =3D=3D BFmode) > > > ? true > > > : default_libgcc_floating_mode_supported_p (mode)); > > > } > > > @@ -22805,9 +22825,10 @@ ix86_emit_support_tinfos (emit_support_tinfo= s_callback callback) > > > > > > if (!TARGET_SSE2) > > > { > > > - gcc_checking_assert (!float16_type_node && !bfloat16_type_node= ); > > > - float16_type_node =3D ix86_float16_type_node; > > > - bfloat16_type_node =3D ix86_bf16_type_node; > > > + if (!float16_type_node) > > > + float16_type_node =3D ix86_float16_type_node; > > > + if (!bfloat16_type_node) > > > + bfloat16_type_node =3D ix86_bf16_type_node; > > > callback (float16_type_node); > > > callback (bfloat16_type_node); > > > float16_type_node =3D NULL_TREE; > > > @@ -24259,6 +24280,86 @@ ix86_init_libfuncs (void) > > > #endif > > > } > > > > > > +/* Return the diagnostic message string if conversion from FROMTYPE = to > > > + TOTYPE is not allowed, NULL otherwise. */ > > > + > > > +static const char * > > > +ix86_invalid_conversion (const_tree fromtype, const_tree totype) > > > +{ > > > + machine_mode from_mode =3D element_mode (fromtype); > > > + machine_mode to_mode =3D element_mode (totype); > > > + > > > + if (!TARGET_SSE2 && from_mode !=3D to_mode) > > > + { > > > + /* Do no allow conversions to/from BFmode/HFmode scalar types > > > + when TARGET_SSE2 is not available. */ > > > + if (from_mode =3D=3D BFmode) > > > + return N_("invalid conversion from type %<__bf16%> " > > > + "without option %<-msse2%>"); > > > + if (from_mode =3D=3D HFmode) > > > + return N_("invalid conversion from type %<_Float16%> " > > > + "without option %<-msse2%>"); > > > + if (to_mode =3D=3D BFmode) > > > + return N_("invalid conversion to type %<__bf16%> " > > > + "without option %<-msse2%>"); > > > + if (to_mode =3D=3D HFmode) > > > + return N_("invalid conversion to type %<_Float16%> " > > > + "without option %<-msse2%>"); > > > + } > > > + > > > + /* Conversion allowed. */ > > > + return NULL; > > > +} > > > + > > > +/* Return the diagnostic message string if the unary operation OP is > > > + not permitted on TYPE, NULL otherwise. */ > > > + > > > +static const char * > > > +ix86_invalid_unary_op (int op, const_tree type) > > > +{ > > > + machine_mode mmode =3D element_mode (type); > > > + /* Reject all single-operand operations on BFmode/HFmode except fo= r & > > > + when TARGET_SSE2 is not available. */ > > > + if (!TARGET_SSE2 && op !=3D ADDR_EXPR) > > > + { > > > + if (mmode =3D=3D BFmode) > > > + return N_("operation not permitted on type %<__bf16%> " > > > + "without option %<-msse2%>"); > > > + if (mmode =3D=3D HFmode) > > > + return N_("operation not permitted on type %<_Float16%> " > > > + "without option %<-msse2%>"); > > > + } > > > + > > > + /* Operation allowed. */ > > > + return NULL; > > > +} > > > + > > > +/* Return the diagnostic message string if the binary operation OP i= s > > > + not permitted on TYPE1 and TYPE2, NULL otherwise. */ > > > + > > > +static const char * > > > +ix86_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, > > > + const_tree type2) > > > +{ > > > + machine_mode type1_mode =3D element_mode (type1); > > > + machine_mode type2_mode =3D element_mode (type2); > > > + /* Reject all 2-operand operations on BFmode or HFmode > > > + when TARGET_SSE2 is not available. */ > > > + if (!TARGET_SSE2) > > > + { > > > + if (type1_mode =3D=3D BFmode || type2_mode =3D=3D BFmode) > > > + return N_("operation not permitted on type %<__bf16%> " > > > + "without option %<-msse2%>"); > > > + > > > + if (type1_mode =3D=3D HFmode || type2_mode =3D=3D HFmode) > > > + return N_("operation not permitted on type %<_Float16%> " > > > + "without option %<-msse2%>"); > > > + } > > > + > > > + /* Operation allowed. */ > > > + return NULL; > > > +} > > > + > > > /* Set the value of FLT_EVAL_METHOD in float.h. When using only the > > > FPU, assume that the fpcw is set to extended precision; when usin= g > > > only SSE, rounding is correct; when using both SSE and the FPU, > > > @@ -25248,6 +25349,15 @@ ix86_libgcc_floating_mode_supported_p > > > #undef TARGET_MEMTAG_TAG_SIZE > > > #define TARGET_MEMTAG_TAG_SIZE ix86_memtag_tag_size > > > > > > +#undef TARGET_INVALID_CONVERSION > > > +#define TARGET_INVALID_CONVERSION ix86_invalid_conversion > > > + > > > +#undef TARGET_INVALID_UNARY_OP > > > +#define TARGET_INVALID_UNARY_OP ix86_invalid_unary_op > > > + > > > +#undef TARGET_INVALID_BINARY_OP > > > +#define TARGET_INVALID_BINARY_OP ix86_invalid_binary_op > > > + > > > static bool ix86_libc_has_fast_function (int fcode ATTRIBUTE_UNUSED) > > > { > > > #ifdef OPTION_GLIBC > > > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h > > > index 1da6dce8e0b..7e839bc5c7e 100644 > > > --- a/gcc/config/i386/i386.h > > > +++ b/gcc/config/i386/i386.h > > > @@ -1046,6 +1046,10 @@ extern const char *host_detect_local_cpu (int = argc, const char **argv); > > > #define VALID_AVX512FP16_REG_MODE(MODE) = \ > > > ((MODE) =3D=3D V8HFmode || (MODE) =3D=3D V16HFmode || (MODE) =3D= =3D V32HFmode) > > > > > > +#define VALID_SSE2_TYPE_MODE(MODE) \ > > > + ((MODE) =3D=3D HFmode || (MODE) =3D=3D BFmode \ > > > + || (MODE) =3D=3D HCmode || (MODE) =3D=3D BCmode) > > > + > > > #define VALID_SSE2_REG_MODE(MODE) = \ > > > ((MODE) =3D=3D V16QImode || (MODE) =3D=3D V8HImode || (MODE) =3D= =3D V2DFmode \ > > > || (MODE) =3D=3D V8HFmode || (MODE) =3D=3D V4HFmode || (MODE) =3D= =3D V2HFmode \ > > > diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.= h > > > index b220d871942..cc78df56940 100644 > > > --- a/gcc/config/i386/immintrin.h > > > +++ b/gcc/config/i386/immintrin.h > > > @@ -98,11 +98,9 @@ > > > > > > #include > > > > > > -#ifdef __SSE2__ > > > #include > > > > > > #include > > > -#endif > > > > > > #include > > > > > > @@ -118,13 +116,11 @@ > > > > > > #include > > > > > > -#ifdef __SSE2__ > > > #include > > > > > > #include > > > > > > #include > > > -#endif > > > > > > #include > > > > > > diff --git a/gcc/testsuite/g++.target/i386/float16-1.C b/gcc/testsuit= e/g++.target/i386/float16-1.C > > > index f96b932b698..938852ee9ad 100644 > > > --- a/gcc/testsuite/g++.target/i386/float16-1.C > > > +++ b/gcc/testsuite/g++.target/i386/float16-1.C > > > @@ -1,8 +1,8 @@ > > > /* { dg-do compile } */ > > > /* { dg-options "-O2 -mno-sse2" } */ > > > > > > -_Float16 /* { dg-error "expected unqualified-id before '_Float= 16'" } */ > > > -foo (_Float16 x) > > > +_Float16 > > > +foo (_Float16 x)/* { dg-error "SSE register return with SSE2 disable= d" } */ > > > { > > > - return x; > > > -} /* { dg-error "'_Float16' is not supported on this ta= rget" } */ > > > + return x;/* { dg-error "SSE register return with SSE2 disabled" ""= { target ia32 } } */ > > > +} > > > diff --git a/gcc/testsuite/gcc.target/i386/pr109504.c b/gcc/testsuite= /gcc.target/i386/pr109504.c > > > new file mode 100644 > > > index 00000000000..fe5bcda10ad > > > --- /dev/null > > > +++ b/gcc/testsuite/gcc.target/i386/pr109504.c > > > @@ -0,0 +1,6 @@ > > > +/* { dg-do compile } */ > > > +/* { dg-options "-O2 -mno-sse" } */ > > > + > > > +#pragma GCC target("sse4.1") > > > +#include > > > +int main(){return 0;} > > > diff --git a/gcc/testsuite/gcc.target/i386/sse2-bfloat16-1.c b/gcc/te= stsuite/gcc.target/i386/sse2-bfloat16-1.c > > > index 612d55be826..717055bc9ad 100644 > > > --- a/gcc/testsuite/gcc.target/i386/sse2-bfloat16-1.c > > > +++ b/gcc/testsuite/gcc.target/i386/sse2-bfloat16-1.c > > > @@ -1,8 +1,8 @@ > > > /* { dg-do compile } */ > > > /* { dg-options "-O2 -mno-sse2" } */ > > > > > > -__bf16/* { dg-error "unknown type name '__bf16'" } */ > > > -foo (__bf16 x) /* { dg-error "unknown type name '__bf16'" } */ > > > -{ > > > - return x; > > > +__bf16 > > > +foo (__bf16 x) /* { dg-error "SSE register return with SSE2 disable= d" } */ > > > +{ /* { dg-error "SSE register return with SSE2 disabled" "" { targe= t ia32 } } */ > > > + return x; /* { dg-error "SSE register return with SSE2 disabled" = "" { target ia32} } */ > > > } > > > diff --git a/gcc/testsuite/gcc.target/i386/sse2-float16-1.c b/gcc/tes= tsuite/gcc.target/i386/sse2-float16-1.c > > > index 1b645eb499d..faf818df75f 100644 > > > --- a/gcc/testsuite/gcc.target/i386/sse2-float16-1.c > > > +++ b/gcc/testsuite/gcc.target/i386/sse2-float16-1.c > > > @@ -1,8 +1,8 @@ > > > /* { dg-do compile } */ > > > /* { dg-options "-O2 -mno-sse2" } */ > > > > > > -_Float16/* { dg-error "is not supported on this target" } */ > > > -foo (_Float16 x) /* { dg-error "is not supported on this target" } *= / > > > -{ > > > - return x; > > > +_Float16 > > > +foo (_Float16 x) /* { dg-error "SSE register return with SSE2 disabl= ed" } */ > > > +{ /* { dg-error "SSE register return with SSE2 disabled" "" { targe= t ia32 } } */ > > > + return x; /* { dg-error "SSE register return with SSE2 disabled" = "" { target ia32} } */ > > > } > > > diff --git a/gcc/testsuite/gcc.target/i386/sse2-float16-4.c b/gcc/tes= tsuite/gcc.target/i386/sse2-float16-4.c > > > new file mode 100644 > > > index 00000000000..64baf92ff56 > > > --- /dev/null > > > +++ b/gcc/testsuite/gcc.target/i386/sse2-float16-4.c > > > @@ -0,0 +1,25 @@ > > > +/* { dg-do compile } */ > > > +/* { dg-options "-O2 -mno-sse2" } */ > > > + > > > +_Float16 a; > > > +__bf16 c; > > > +_Complex _Float16 ac; > > > + > > > +void > > > +foo (_Float16* p) > > > +{ > > > + a =3D *p; > > > +} > > > + > > > +void > > > +foo1 (__bf16 *p) > > > +{ > > > + c =3D *p; > > > +} > > > + > > > + > > > +void > > > +foo2 (_Complex _Float16* p) > > > +{ > > > + ac =3D *p; > > > +} > > > diff --git a/gcc/testsuite/gcc.target/i386/sse2-float16-5.c b/gcc/tes= tsuite/gcc.target/i386/sse2-float16-5.c > > > new file mode 100644 > > > index 00000000000..c3ed23b8ab3 > > > --- /dev/null > > > +++ b/gcc/testsuite/gcc.target/i386/sse2-float16-5.c > > > @@ -0,0 +1,24 @@ > > > +/* { dg-do compile { target ia32} } */ > > > +/* { dg-options "-O2 -mno-sse2" } */ > > > + > > > +_Float16 a; > > > +__bf16 c; > > > +_Complex ac; > > > +void > > > +foo (_Float16 p) > > > +{ > > > + a =3D p; > > > +} > > > + > > > +void > > > +foo1 (__bf16 p) > > > +{ > > > + c =3D p; > > > +} > > > + > > > + > > > +void > > > +foo2 (_Complex p) > > > +{ > > > + ac =3D p; > > > +} > > > diff --git a/libgcc/config/i386/t-softfp b/libgcc/config/i386/t-softf= p > > > index 69d0f819822..80d1fac121b 100644 > > > --- a/libgcc/config/i386/t-softfp > > > +++ b/libgcc/config/i386/t-softfp > > > @@ -31,3 +31,10 @@ CFLAGS-trunchfbf2.c +=3D -msse2 > > > CFLAGS-eqhf2.c +=3D -msse2 > > > CFLAGS-_divhc3.c +=3D -msse2 > > > CFLAGS-_mulhc3.c +=3D -msse2 > > > + > > > +CFLAGS-_hf_to_sd.c +=3D -msse2 > > > +CFLAGS-_hf_to_dd.c +=3D -msse2 > > > +CFLAGS-_hf_to_td.c +=3D -msse2 > > > +CFLAGS-_sd_to_hf.c +=3D -msse2 > > > +CFLAGS-_dd_to_hf.c +=3D -msse2 > > > +CFLAGS-_td_to_hf.c +=3D -msse2 > > > -- > > > 2.39.1.388.g2fc9e9ca3c > > > > > > > > > -- > > BR, > > Hongtao > > > > -- > BR, > Hongtao