From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28911 invoked by alias); 12 Nov 2017 16:29:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 28902 invoked by uid 89); 12 Nov 2017 16:29:37 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.0 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=cosmetic, bellow, opens X-HELO: mail-it0-f54.google.com Received: from mail-it0-f54.google.com (HELO mail-it0-f54.google.com) (209.85.214.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 12 Nov 2017 16:29:36 +0000 Received: by mail-it0-f54.google.com with SMTP id n134so3088981itg.1 for ; Sun, 12 Nov 2017 08:29:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=RoSETCNyVJBhcdbg8W+31fuH8WyO2g/baI/bt05l67E=; b=rp/VzWplIaVj1R4HS2nI7CVF9TMpN+JscB1saPuMYTFfd+ZU99horbGYCu8O9veYUE 0mtZGH8zIwaC+ctKZBxRvUnD7NEtzwdAZTMEkQoAeBrpDvhb+H0OMWEXLnQwRr5F2iWK 96ETBvXPbKYvNz3I3t/ETEblqV2JDiDkIFkzgZFQ9NKSG368jGfq/PKs9vmnhFUT4w+5 0G7hfKx70CeMDveWMUPrabr5C88+I4aXwZXwd8L53XXNsYmbekAN0LlHOEL6Xs25jMUo kXUsoY0+wdvKjtXZKmU75ArbgK0tHSIXnKn4N4XrccN5K35nDrpwT2QbNm3sK701qoZF CnUA== X-Gm-Message-State: AJaThX5L2lnEZTjh/uTgbUvSekeflYVpt8l3cd6tugFNxNh3m4pPm+ez R9eU2RI1ZG2npeiXziKt8yoSui0KQXQ0EBRnr44= X-Google-Smtp-Source: AGs4zMbjLBuFCCtn0veQPh8c2Zo/RJeltDu0V/cQplfakwpOXvpl3OZ7iH9gAjoUV9x5vnTftwvL9ViNbx0GSlofYx0= X-Received: by 10.36.87.2 with SMTP id u2mr7771129ita.151.1510504174169; Sun, 12 Nov 2017 08:29:34 -0800 (PST) MIME-Version: 1.0 Received: by 10.2.156.105 with HTTP; Sun, 12 Nov 2017 08:29:33 -0800 (PST) In-Reply-To: <4E89A029A0F8D443B436A5167BA3C53F42ACE34D@IRSMSX101.ger.corp.intel.com> References: <4E89A029A0F8D443B436A5167BA3C53F42ACE34D@IRSMSX101.ger.corp.intel.com> From: Uros Bizjak Date: Sun, 12 Nov 2017 16:34:00 -0000 Message-ID: Subject: Re: [patch][x86] -march=icelake To: "Koval, Julia" Cc: GCC Patches , Kirill Yukhin Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2017-11/txt/msg00944.txt.bz2 On Sun, Nov 12, 2017 at 1:04 AM, Koval, Julia wrote: > Hi, this patch adds new option -march=icelake. Isasets defined in: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > I didn't add arch code to driver-i386.c, because there is no code available in SDM yet, only for cannonlake (https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf Chapter 2). This means the driver will go through generic detection for -march=native. Perhaps a comment should be added, so we won't forget to add the model number when one is available. > gcc/ > * config.gcc: Add -march=icelake. > * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake. > * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake. > * config/i386/i386.c (processor_costs): Add m_ICELAKE. > (PTA_ICELAKE, PTA2_ICELAKE, PTA2_GFNI, PTA2_AVX512VBMI2, PTA2_VAES, > PTA2_AVX512VNNI, PTA2_VPCLMULQDQ, PTA2_RDPID, PTA2_AVX512BITALG): New. > (processor_target_table): Add icelake. > (ix86_option_override_internal): Add flags2 for new PTA, handle GFNI, RDPID. > (get_builtin_code_for_version): Handle icelake. > (M_INTEL_COREI7_ICELAKE): New. > * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New. > * doc/invoke.texi: Add -march=icelake. > gcc/testsuite/ > * gcc.target/i386/funcspec-56.inc: Handle new march. > * g++.dg/ext/mv16.C: Ditto. > libgcc/ > * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE. @@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p, #define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61) #define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62) #define PTA_SGX (HOST_WIDE_INT_1 << 63) +#define PTA2_GFNI (HOST_WIDE_INT_1 << 0) +#define PTA2_AVX512VBMI2 (HOST_WIDE_INT_1 << 1) +#define PTA2_VAES (HOST_WIDE_INT_1 << 2) +#define PTA2_AVX512VNNI (HOST_WIDE_INT_1 << 3) +#define PTA2_VPCLMULQDQ (HOST_WIDE_INT_1 << 4) +#define PTA2_RDPID (HOST_WIDE_INT_1 << 5) +#define PTA2_AVX512BITALG (HOST_WIDE_INT_1 << 6) Please add these options first. On a related note, there should probably be a better way to extend various bitmapped flag variables beyond 64bit words. We are constantly going over 64bit sizes in target option masks, now the number of processor flags doesn't fit in a word anymore. There are several places one has to keep in mind in which word some specific flag lives, and this approach opens several ways to make a hard to detect mistake. Does C++ offer a more elegant way? Bellow, please find a suggestion of a couple of cosmetic changes. Thanks, Uros. @@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p, #define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61) #define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62) #define PTA_SGX (HOST_WIDE_INT_1 << 63) Please add a comment here, that the folowing belongs to flags2. +#define PTA2_GFNI (HOST_WIDE_INT_1 << 0) +#define PTA2_AVX512VBMI2 (HOST_WIDE_INT_1 << 1) +#define PTA2_VAES (HOST_WIDE_INT_1 << 2) @@ -4105,6 +4124,12 @@ ix86_option_override_internal (bool main_args_p, if (processor_alias_table[i].flags & PTA_SGX && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX; Please add vertical space here to visually separate flags and flags2 processing. + if (processor_alias_table[i].flags2 & PTA2_RDPID + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;