From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 1881 invoked by alias); 14 Oct 2014 18:34:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 1870 invoked by uid 89); 14 Oct 2014 18:34:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f181.google.com Received: from mail-lb0-f181.google.com (HELO mail-lb0-f181.google.com) (209.85.217.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 14 Oct 2014 18:34:23 +0000 Received: by mail-lb0-f181.google.com with SMTP id l4so8563405lbv.40 for ; Tue, 14 Oct 2014 11:34:19 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.112.57.227 with SMTP id l3mr7241399lbq.68.1413311659063; Tue, 14 Oct 2014 11:34:19 -0700 (PDT) Received: by 10.152.8.103 with HTTP; Tue, 14 Oct 2014 11:34:19 -0700 (PDT) In-Reply-To: <20141014071820.GA59591@msticlxl57.ims.intel.com> References: <20140925141206.GB27825@msticlxl57.ims.intel.com> <20141014071820.GA59591@msticlxl57.ims.intel.com> Date: Tue, 14 Oct 2014 18:37:00 -0000 Message-ID: Subject: Re: [PATCH i386 AVX512] [56/n] Add plus/minus/abs/neg/andnot insn patterns. From: Uros Bizjak To: Kirill Yukhin Cc: Jakub Jelinek , Richard Henderson , GCC Patches Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SW-Source: 2014-10/txt/msg01284.txt.bz2 On Tue, Oct 14, 2014 at 9:18 AM, Kirill Yukhin wr= ote: > Hello Uro=C5=A1, > It seems like I missed to post uppdated patch. > On 25 Sep 20:11, Uros Bizjak wrote: >> I'd rather go with the second approach, it is less confusing from the >> maintainer POV. All other patterns with masking use some consistent >> template, so I'd suggest using the same approach for everything. If it >> is indeed too many patterns, then please split the patch to smaller >> pieces. > Goal was not to decrease size of the patch, I wanted to make pattern look > simpler by hiding masking stuff beyond `subst'. > Anyway, I've updated the patch. > > Here it is (bootstrapped and regtested). > > Is it ok for trunk? > > gcc/ > * config/i386/sse.md (define_mode_iterator VI_AVX2): Extend > to support AVX-512BW. > (define_mode_iterator VI124_AVX2_48_AVX512F): Remove. > (define_expand "3"): Remove masking support. > (define_insn "*3"): Ditto. > (define_expand "3_mask"): New. > (define_expand "3_mask"): Dit= to. > (define_insn "*3_mask"): Ditt= o. > (define_insn "*3_mask"): Ditt= o. > (define_expand "_andnot3"): Remove masking suppo= rt. > (define_insn "*andnot3"): Ditto. > (define_expand "_andnot3_mask"): N= ew. > (define_expand "_andnot3_mask"): D= itto. > (define_insn "*andnot3"): Ditto. > (define_insn "*andnot3"): Ditto. > (define_insn "*abs2"): Remove masking support. > (define_insn "abs2_mask"): New. > (define_insn "abs2_mask"): Ditto. > (define_expand "abs2"): Use VI_AVX2 mode iterator. IMO, it seems much more readable this way. OK for mainline. Thanks, Uros.