* [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
@ 2017-11-13 17:37 Shalnov, Sergey
2017-11-13 20:23 ` Uros Bizjak
2017-11-14 19:38 ` Sandra Loosemore
0 siblings, 2 replies; 10+ messages in thread
From: Shalnov, Sergey @ 2017-11-13 17:37 UTC (permalink / raw)
To: 'gcc-patches@gcc.gnu.org'
Cc: 'kirill.yukhin@gmail.com', 'ubizjak@gmail.com',
Koval, Julia, Senkevich, Andrew, Peryt, Sebastian, Ivchenko,
Alexander
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Hi,
Modern architectures provides wider and wider vector registers. This patch implements
common (in i386 arch) option to prefer vector register width for the vectorizer.
Currently, GCC has "-mprefer-avx128" and "-mprefer-avx256" options to limit maximum
vector register width in vectorizer. To avoid feature implementation of further options
like "-mprefer-avx512", "-mprefer-avx1024", etc. I propose to implement
the option "-mprefer-vector-width=[none|128|256|512]".
Also I propose to remove recently added -mprefer-avx256 option in favor
of -mprefer-vector-width=256 and consider also make -mprefer-avx128 as deprecated.
Latter one is already there for few years, so It might be better to keep it as
deprecated for some time.
2017-11-13 Sergey Shalnov <Sergey.Shalnov@intel.com>
gcc/
* config/i386/i386-opts.h (enum prefer_vector_width): Added new enum
for the new option -mprefer-vector-width=[none|128|256|512].
* config/i386/i386.c (ix86_target_string): remove old style
-mprefer-avx128 and -mprefer-avx256 options.
(ix86_option_override_internal): Apply defaults for the
-mprefer-vector-width=[128|256] option.
* config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256):
Implement macros to work with -mprefer-vector-width=.
* config/i386/i386.opt: Implemented option
-mprefer-vector-width=[none|128|256|512].
* doc/invoke.texi: Documentation for
-mprefer-vector-width=[none|128|256|512].
gcc/testsuite/
* g++.dg/ext/pr57362.C (__attribute__): Apply new option syntax.
* g++.dg/torture/pr81249.C: Ditto.
* gcc.dg/torture/pr66076.c: Ditto.
* gcc.target/i386/avx-cvt-3.c: Ditto.
* gcc.target/i386/avx2-vpaddb-3.c: Ditto.
* gcc.target/i386/avx2-vpaddd-3.c: Ditto.
* gcc.target/i386/avx2-vpaddq-3.c: Ditto.
* gcc.target/i386/avx2-vpaddw-3.c: Ditto.
* gcc.target/i386/avx2-vpand-3.c: Ditto.
* gcc.target/i386/avx2-vpmulld-3.c: Ditto.
* gcc.target/i386/avx2-vpmullw-3.c: Ditto.
* gcc.target/i386/avx2-vpsrad-3.c: Ditto.
* gcc.target/i386/avx2-vpsraw-3.c: Ditto.
* gcc.target/i386/avx2-vpsrld-3.c: Ditto.
* gcc.target/i386/avx2-vpsrlw-3.c: Ditto.
* gcc.target/i386/avx2-vpsubb-3.c: Ditto.
* gcc.target/i386/avx2-vpsubd-3.c: Ditto.
* gcc.target/i386/avx2-vpsubq-3.c: Ditto.
* gcc.target/i386/avx2-vpsubw-3.c: Ditto.
* gcc.target/i386/avx256-unaligned-load-1.c: Ditto.
* gcc.target/i386/avx256-unaligned-load-2.c: Ditto.
* gcc.target/i386/avx256-unaligned-load-4.c: Ditto.
* gcc.target/i386/avx256-unaligned-store-1.c: Ditto.
* gcc.target/i386/avx256-unaligned-store-2.c: Ditto.
* gcc.target/i386/avx256-unaligned-store-4.c: Ditto.
* gcc.target/i386/avx512f-constant-float-return.c: Ditto.
* gcc.target/i386/avx512f-prefer.c: Ditto.
* gcc.target/i386/pr82460-2.c: Ditto.
* gfortran.dg/vect/fast-math-mgrid-resid.f: Ditto.
Sergey
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From 25d6282c9fbe7e8d21d1db7ca5d31a2cdaa25348 Mon Sep 17 00:00:00 2001
From: Sergey Shalnov <Sergey.Shalnov@intel.com>
Date: Sat, 11 Nov 2017 15:01:26 +0300
Subject: [PATCH 1/1] Refactoring options mprefer-avx[128|256] into one
mprefer-vector-width
---
gcc/config/i386/i386-opts.h | 7 ++++++
gcc/config/i386/i386.c | 17 ++++++-------
gcc/config/i386/i386.h | 5 ++++
gcc/config/i386/i386.opt | 29 ++++++++++++++++++----
gcc/doc/invoke.texi | 27 +++++++++++++-------
gcc/testsuite/g++.dg/ext/pr57362.C | 4 +--
gcc/testsuite/g++.dg/torture/pr81249.C | 2 +-
gcc/testsuite/gcc.dg/torture/pr66076.c | 2 +-
gcc/testsuite/gcc.target/i386/avx-cvt-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpand-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c | 2 +-
gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c | 2 +-
.../gcc.target/i386/avx256-unaligned-load-1.c | 2 +-
.../gcc.target/i386/avx256-unaligned-load-2.c | 2 +-
.../gcc.target/i386/avx256-unaligned-load-4.c | 2 +-
.../gcc.target/i386/avx256-unaligned-store-1.c | 2 +-
.../gcc.target/i386/avx256-unaligned-store-2.c | 2 +-
.../gcc.target/i386/avx256-unaligned-store-4.c | 2 +-
.../i386/avx512f-constant-float-return.c | 2 +-
gcc/testsuite/gcc.target/i386/avx512f-prefer.c | 2 +-
gcc/testsuite/gcc.target/i386/pr82460-2.c | 2 +-
.../gfortran.dg/vect/fast-math-mgrid-resid.f | 2 +-
34 files changed, 92 insertions(+), 53 deletions(-)
diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h
index 542cd0f..8c37a74 100644
--- a/gcc/config/i386/i386-opts.h
+++ b/gcc/config/i386/i386-opts.h
@@ -99,4 +99,11 @@ enum stack_protector_guard {
SSP_GLOBAL /* global canary */
};
+enum prefer_vector_width {
+ PVW_NONE,
+ PVW_AVX128,
+ PVW_AVX256,
+ PVW_AVX512
+};
+
#endif
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d9d3709..cb7c28c 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2846,15 +2846,13 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
{ "-mstv", MASK_STV },
{ "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD },
{ "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE },
- { "-mprefer-avx128", MASK_PREFER_AVX128 },
{ "-mcall-ms2sysv-xlogues", MASK_CALL_MS2SYSV_XLOGUES }
};
/* Additional flag options. */
static struct ix86_target_opts flag2_opts[] =
{
- { "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY },
- { "-mprefer-avx256", OPTION_MASK_PREFER_AVX256 },
+ { "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY }
};
const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (isa2_opts)
@@ -4687,14 +4685,15 @@ ix86_option_override_internal (bool main_args_p,
/* Enable 128-bit AVX instruction generation
for the auto-vectorizer. */
if (TARGET_AVX128_OPTIMAL
- && !(opts_set->x_target_flags & MASK_PREFER_AVX128))
- opts->x_target_flags |= MASK_PREFER_AVX128;
- /* Use 256-bit AVX instructions instead of 512-bit AVX instructions
+ && (opts_set->x_prefer_vector_width_type == PVW_NONE)
+ && (opts_set->x_prefer_vector_width_type != PVW_AVX128))
+ opts->x_prefer_vector_width_type = PVW_AVX128;
+ /* Use 256-bit AVX instruction generation
in the auto-vectorizer. */
if (ix86_tune_features[X86_TUNE_AVX256_OPTIMAL]
- && !(opts_set->x_ix86_target_flags & OPTION_MASK_PREFER_AVX256))
- opts->x_ix86_target_flags |= OPTION_MASK_PREFER_AVX256;
-
+ && (opts_set->x_prefer_vector_width_type == PVW_NONE)
+ && (opts_set->x_prefer_vector_width_type != PVW_AVX256))
+ opts->x_prefer_vector_width_type = PVW_AVX256;
if (opts->x_ix86_recip_name)
{
char *p = ASTRDUP (opts->x_ix86_recip_name);
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 837906b..0bbca78 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2671,6 +2671,11 @@ extern void debug_dispatch_window (int);
#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
+/* Use 128-bit AVX instructions in the auto-vectorizer. */
+#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
+/* Use 256-bit AVX instructions in the auto-vectorizer. */
+#define TARGET_PREFER_AVX256 (prefer_vector_width_type == PVW_AVX256)
+
#define IX86_HLE_ACQUIRE (1 << 16)
#define IX86_HLE_RELEASE (1 << 17)
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index d2c10ab..98209cf 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -182,6 +182,10 @@ int x_ix86_tune_no_default
TargetSave
enum ix86_veclibabi x_ix86_veclibabi_type
+;; -mprefer-vector-width=
+TargetSave
+enum prefer_vector_width x_prefer_vector_width_type
+
;; x86 options
m128bit-long-double
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
@@ -588,12 +592,27 @@ Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
or znver1 and Haifa scheduling is selected.
mprefer-avx128
-Target Report Mask(PREFER_AVX128) Save
-Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
+Target Undocumented Warn(%<-mmprefer-avx128%> is deprecated; use %<-mprefer-vector-width=128%> instead)
+
+mprefer-vector-width=
+Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE)
+Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
+
+Enum
+Name(prefer_vector_width) Type(enum prefer_vector_width)
+Known preferred register vector length (to use with the -mprefer-vector-width= option)
+
+EnumValue
+Enum(prefer_vector_width) String(none) Value(PVW_NONE)
+
+EnumValue
+Enum(prefer_vector_width) String(128) Value(PVW_AVX128)
-mprefer-avx256
-Target Report Mask(PREFER_AVX256) Var(ix86_target_flags) Save
-Use 256-bit AVX instructions instead of 512-bit AVX instructions in the auto-vectorizer.
+EnumValue
+Enum(prefer_vector_width) String(256) Value(PVW_AVX256)
+
+EnumValue
+Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
;; ISA support
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 4427328..bc9eb85 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1196,7 +1196,7 @@ See RS/6000 and PowerPC Options.
-mincoming-stack-boundary=@var{num} @gol
-mcld -mcx16 -msahf -mmovbe -mcrc32 @gol
-mrecip -mrecip=@var{opt} @gol
--mvzeroupper -mprefer-avx128 -mprefer-avx256 @gol
+-mvzeroupper -mprefer-vector-width=@var{opt} @gol
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -mavx512vl @gol
-mavx512bw -mavx512dq -mavx512ifma -mavx512vbmi -msha -maes @gol
@@ -26087,15 +26087,24 @@ before a transfer of control flow out of the function to minimize
the AVX to SSE transition penalty as well as remove unnecessary @code{zeroupper}
intrinsics.
-@item -mprefer-avx128
-@opindex mprefer-avx128
-This option instructs GCC to use 128-bit AVX instructions instead of
-256-bit AVX instructions in the auto-vectorizer.
+@item -mprefer-vector-width=@var{opt}
+@opindex mprefer-vector-width
+This option instructs GCC to use @var{opt}-bit vector width in instructions
+instead of default on the selected platform.
-@item -mprefer-avx256
-@opindex mprefer-avx256
-This option instructs GCC to use 256-bit AVX instructions instead of
-512-bit AVX instructions in the auto-vectorizer.
+@table @samp
+@item none
+No extra limitations applied to GCC over than defined by the selected platform.
+
+@item 128
+Prefer 128-bit vector width for instructions.
+
+@item 256
+Prefer 256-bit vector width for instructions.
+
+@item 512
+Prefer 512-bit vector width for instructions.
+@end table
@item -mcx16
@opindex mcx16
diff --git a/gcc/testsuite/g++.dg/ext/pr57362.C b/gcc/testsuite/g++.dg/ext/pr57362.C
index 3613b63..c9b3119 100644
--- a/gcc/testsuite/g++.dg/ext/pr57362.C
+++ b/gcc/testsuite/g++.dg/ext/pr57362.C
@@ -79,9 +79,9 @@ __attribute__((target("vzeroupper")))
int foo(void) { return 1; }
__attribute__((target("dispatch-scheduler")))
int foo(void) { return 1; }
-__attribute__((target("prefer-avx128")))
+__attribute__((target("prefer-vector-width=128")))
int foo(void) { return 1; }
-__attribute__((target("prefer-avx256")))
+__attribute__((target("prefer-vector-width=256")))
int foo(void) { return 1; }
__attribute__((target("32")))
int foo(void) { return 1; }
diff --git a/gcc/testsuite/g++.dg/torture/pr81249.C b/gcc/testsuite/g++.dg/torture/pr81249.C
index 7bf617b..5af319d 100644
--- a/gcc/testsuite/g++.dg/torture/pr81249.C
+++ b/gcc/testsuite/g++.dg/torture/pr81249.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-mavx2 -mprefer-avx128" { target x86_64-*-* i?86-*-* } } */
+/* { dg-additional-options "-mavx2 -mprefer-vector-width=128" { target x86_64-*-* i?86-*-* } } */
typedef struct rtx_def *rtx;
union rtunion {
diff --git a/gcc/testsuite/gcc.dg/torture/pr66076.c b/gcc/testsuite/gcc.dg/torture/pr66076.c
index 7e7d34d..160259f 100644
--- a/gcc/testsuite/gcc.dg/torture/pr66076.c
+++ b/gcc/testsuite/gcc.dg/torture/pr66076.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "" } */
-/* { dg-options "-mno-prefer-avx128 -march=bdver4" { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-mprefer-vector-width=256 -march=bdver4" { target i?86-*-* x86_64-*-* } } */
void
f0a (char *result, char *arg1, char *arg4, char temp_6)
diff --git a/gcc/testsuite/gcc.target/i386/avx-cvt-3.c b/gcc/testsuite/gcc.target/i386/avx-cvt-3.c
index de2e482..34cf053 100644
--- a/gcc/testsuite/gcc.target/i386/avx-cvt-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx-cvt-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mavx -mno-avx2 -mtune=generic -mprefer-avx128 -fdump-tree-vect-details" } */
+/* { dg-options "-O3 -mavx -mno-avx2 -mtune=generic -mprefer-vector-width=128 -fdump-tree-vect-details" } */
#include "avx-cvt-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
index 0051443..c3cef08 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddb-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c
index 39567f6c..2872fa1 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddd-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
index d9b8612..39f28c0 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddq-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
index feb2b1f..d8e0da6 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpaddw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c
index 37b8d24..d946f91 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpand-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c
index da273ae..c4f500b 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpmulld-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
index 47b52b9..7d02ecf 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpmullw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c
index ea2e908..92ada7b 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrad-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
index 8331a48..da27009 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsraw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c
index ea2e908..92ada7b 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrld-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
index bea761f..a9b58ff 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsrlw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
index ae64e65..d1b3e00 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubb-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c
index 50055ad..21b2d2f 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubd-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
index 6f3ce1f..0ca50ea 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubq-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c b/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
index b2b01d1..31b53b8 100644
--- a/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx2-vpsubw-3.c
@@ -1,5 +1,5 @@
/* { dg-do run } */
-/* { dg-options "-mavx2 -mno-prefer-avx128 -O2 -ftree-vectorize -save-temps" } */
+/* { dg-options "-mavx2 -mprefer-vector-width=256 -O2 -ftree-vectorize -save-temps" } */
/* { dg-require-effective-target avx2 } */
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
index 7115b0a..acd3ba2 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mno-prefer-avx128" } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mprefer-vector-width=256" } */
#define N 1024
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
index 6802b74..31fe15e 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mno-prefer-avx128" } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-load -mprefer-vector-width=256" } */
void
avx_test (char **cp, char **ep)
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
index dcd630d..216d850 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -mno-prefer-avx128 -fno-common" } */
+/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -mprefer-vector-width=256 -fno-common" } */
#define N 1024
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
index 4c71395..f22e001 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mno-prefer-avx128 -fno-common" } */
+/* { dg-options "-O3 -dp -mavx -mavx256-split-unaligned-store -mprefer-vector-width=256 -fno-common" } */
#define N 1024
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
index a2b644e..5b70618 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O3 -mtune-ctrl=sse_typeless_stores -dp -mavx -mavx256-split-unaligned-store -mno-prefer-avx128" } */
+/* { dg-options "-O3 -mtune-ctrl=sse_typeless_stores -dp -mavx -mavx256-split-unaligned-store -mprefer-vector-width=256" } */
#define N 1024
diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
index c4566a3..a6cbe89 100644
--- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
+++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -mno-prefer-avx128 -fno-common" } */
+/* { dg-options "-O3 -dp -mavx -mno-avx256-split-unaligned-load -mno-avx256-split-unaligned-store -mprefer-vector-width=256 -fno-common" } */
#define N 1024
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
index 153cf69..ed0becc 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
float
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-prefer.c b/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
index defe51e..a74ce07 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
/* { dg-final { scan-assembler "vmulpd" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr82460-2.c b/gcc/testsuite/gcc.target/i386/pr82460-2.c
index 4d96521..d374b1f 100644
--- a/gcc/testsuite/gcc.target/i386/pr82460-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr82460-2.c
@@ -1,6 +1,6 @@
/* PR target/82460 */
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mno-prefer-avx256" } */
+/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mprefer-vector-width=512" } */
/* We want to reuse the permutation mask in the loop, so use vpermt2b rather
than vpermi2b. */
/* { dg-final { scan-assembler-not {\mvpermi2b\M} } } */
diff --git a/gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f b/gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f
index 2e0840d..cd85291 100644
--- a/gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f
+++ b/gcc/testsuite/gfortran.dg/vect/fast-math-mgrid-resid.f
@@ -1,7 +1,7 @@
! { dg-do compile }
! { dg-require-effective-target vect_double }
! { dg-options "-O3 --param vect-max-peeling-for-alignment=0 -fpredictive-commoning -fdump-tree-pcom-details" }
-! { dg-additional-options "-mprefer-avx128" { target { i?86-*-* x86_64-*-* } } }
+! { dg-additional-options "-mprefer-vector-width=128" { target { i?86-*-* x86_64-*-* } } }
! { dg-additional-options "-mzarch" { target { s390*-*-* } } }
******* RESID COMPUTES THE RESIDUAL: R = V - AU
--
1.8.3.1
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-13 17:37 [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512] Shalnov, Sergey
@ 2017-11-13 20:23 ` Uros Bizjak
2017-11-13 20:32 ` Uros Bizjak
2017-11-13 23:41 ` Joseph Myers
2017-11-14 19:38 ` Sandra Loosemore
1 sibling, 2 replies; 10+ messages in thread
From: Uros Bizjak @ 2017-11-13 20:23 UTC (permalink / raw)
To: Shalnov, Sergey
Cc: gcc-patches, kirill.yukhin, Koval, Julia, Senkevich, Andrew,
Peryt, Sebastian, Ivchenko, Alexander
On Mon, Nov 13, 2017 at 6:25 PM, Shalnov, Sergey
<sergey.shalnov@intel.com> wrote:
> Hi,
> Modern architectures provides wider and wider vector registers. This patch implements
> common (in i386 arch) option to prefer vector register width for the vectorizer.
> Currently, GCC has "-mprefer-avx128" and "-mprefer-avx256" options to limit maximum
> vector register width in vectorizer. To avoid feature implementation of further options
> like "-mprefer-avx512", "-mprefer-avx1024", etc. I propose to implement
> the option "-mprefer-vector-width=[none|128|256|512]".
>
> Also I propose to remove recently added -mprefer-avx256 option in favor
> of -mprefer-vector-width=256 and consider also make -mprefer-avx128 as deprecated.
> Latter one is already there for few years, so It might be better to keep it as
> deprecated for some time.
This is a good idea, but please mark -mprefer-avx128 "RejectNegative
Alias(mprefer-vector-width=, 128)". IMO, we can leave this option as
is, no need to deprecate it, or warn about its usage. Using Alias
keyword, it will be just a shortcut for -mprefer-vector-width=128.
[BTW: --mprefer-avx128 should be marked RejectNegative from the
beginning; let's just assume nobody uses it in its (somehow weird)
negative "-mno-prefer-avx128" form.]
Uros.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-13 20:23 ` Uros Bizjak
@ 2017-11-13 20:32 ` Uros Bizjak
2017-11-13 23:41 ` Joseph Myers
1 sibling, 0 replies; 10+ messages in thread
From: Uros Bizjak @ 2017-11-13 20:32 UTC (permalink / raw)
To: Shalnov, Sergey
Cc: gcc-patches, kirill.yukhin, Koval, Julia, Senkevich, Andrew,
Peryt, Sebastian, Ivchenko, Alexander
On Mon, Nov 13, 2017 at 9:13 PM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Mon, Nov 13, 2017 at 6:25 PM, Shalnov, Sergey
> <sergey.shalnov@intel.com> wrote:
>> Hi,
>> Modern architectures provides wider and wider vector registers. This patch implements
>> common (in i386 arch) option to prefer vector register width for the vectorizer.
>> Currently, GCC has "-mprefer-avx128" and "-mprefer-avx256" options to limit maximum
>> vector register width in vectorizer. To avoid feature implementation of further options
>> like "-mprefer-avx512", "-mprefer-avx1024", etc. I propose to implement
>> the option "-mprefer-vector-width=[none|128|256|512]".
>>
>> Also I propose to remove recently added -mprefer-avx256 option in favor
>> of -mprefer-vector-width=256 and consider also make -mprefer-avx128 as deprecated.
>> Latter one is already there for few years, so It might be better to keep it as
>> deprecated for some time.
>
> This is a good idea, but please mark -mprefer-avx128 "RejectNegative
> Alias(mprefer-vector-width=, 128)". IMO, we can leave this option as
> is, no need to deprecate it, or warn about its usage. Using Alias
> keyword, it will be just a shortcut for -mprefer-vector-width=128.
>
> [BTW: --mprefer-avx128 should be marked RejectNegative from the
> beginning; let's just assume nobody uses it in its (somehow weird)
> negative "-mno-prefer-avx128" form.]
... or we can simply mark -mprefer-avx128 with
Alias(mprefer-vector-width=, 128, 256) to keep it 100% backward
compatible.
Uros.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-13 20:23 ` Uros Bizjak
2017-11-13 20:32 ` Uros Bizjak
@ 2017-11-13 23:41 ` Joseph Myers
2017-11-14 8:31 ` Uros Bizjak
1 sibling, 1 reply; 10+ messages in thread
From: Joseph Myers @ 2017-11-13 23:41 UTC (permalink / raw)
To: Uros Bizjak
Cc: Shalnov, Sergey, gcc-patches, kirill.yukhin, Koval, Julia,
Senkevich, Andrew, Peryt, Sebastian, Ivchenko, Alexander
On Mon, 13 Nov 2017, Uros Bizjak wrote:
> [BTW: --mprefer-avx128 should be marked RejectNegative from the
> beginning; let's just assume nobody uses it in its (somehow weird)
> negative "-mno-prefer-avx128" form.]
It's used in that form in various testcases that otherwise fail when GCC
is configured --with-arch= some CPU that defaults to -mprefer-avx128.
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-13 23:41 ` Joseph Myers
@ 2017-11-14 8:31 ` Uros Bizjak
2017-11-21 16:07 ` Shalnov, Sergey
0 siblings, 1 reply; 10+ messages in thread
From: Uros Bizjak @ 2017-11-14 8:31 UTC (permalink / raw)
To: Joseph Myers
Cc: Shalnov, Sergey, gcc-patches, kirill.yukhin, Koval, Julia,
Senkevich, Andrew, Peryt, Sebastian, Ivchenko, Alexander
On Tue, Nov 14, 2017 at 12:14 AM, Joseph Myers <joseph@codesourcery.com> wrote:
> On Mon, 13 Nov 2017, Uros Bizjak wrote:
>
>> [BTW: --mprefer-avx128 should be marked RejectNegative from the
>> beginning; let's just assume nobody uses it in its (somehow weird)
>> negative "-mno-prefer-avx128" form.]
>
> It's used in that form in various testcases that otherwise fail when GCC
> is configured --with-arch= some CPU that defaults to -mprefer-avx128.
In this case, an even better choice would be:
Alias(mprefer-vector-width=, 128, none)
So, -mno-prefer-avx128 would just set the default back to none.
Uros.
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-14 8:31 ` Uros Bizjak
@ 2017-11-21 16:07 ` Shalnov, Sergey
2017-11-21 17:19 ` Uros Bizjak
0 siblings, 1 reply; 10+ messages in thread
From: Shalnov, Sergey @ 2017-11-21 16:07 UTC (permalink / raw)
To: Uros Bizjak
Cc: gcc-patches, kirill.yukhin, Koval, Julia, Senkevich, Andrew,
Peryt, Sebastian, Ivchenko, Alexander, Joseph Myers
[-- Attachment #1: Type: text/plain, Size: 2661 bytes --]
Uros,
I did new patch with all comments addressed as proposed.
1. old option -mprefer-avx128 is Alias(mprefer-vector-width=, 128, none)
2. Simplified default initialization (as Bernhard proposed)
3. Fixed documentation (proposed by Sandra)
4. Several tests are changed to use new style of the option but many leaved with -mprefer-avx128 (one test with new style -mprefer-vector-width=128)
2017-11-21 Sergey Shalnov <Sergey.Shalnov@intel.com>
gcc/
* config/i386/i386-opts.h (enum prefer_vector_width): Added new enum
for the new option -mprefer-vector-width=[none|128|256|512].
* config/i386/i386.c (ix86_target_string): remove old style options
-mprefer-avx256 and make -mprefer-avx128 as alias.
(ix86_option_override_internal): Apply defaults for the
-mprefer-vector-width=[128|256] option.
* config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256):
Implement macros to work with -mprefer-vector-width=.
* config/i386/i386.opt: Implemented option
-mprefer-vector-width=[none|128|256|512].
* doc/invoke.texi: Documentation for
-mprefer-vector-width=[none|128|256|512].
gcc/testsuite/
* g++.dg/ext/pr57362.C (__attribute__): Apply new option syntax.
* g++.dg/torture/pr81249.C: Ditto.
* gcc.target/i386/avx512f-constant-float-return.c: Ditto.
* gcc.target/i386/avx512f-prefer.c: Ditto.
* gcc.target/i386/pr82460-2.c: Ditto.
Please merge this patch if you think it is acceptable.
Thank you
Sergey
-----Original Message-----
From: Uros Bizjak [mailto:ubizjak@gmail.com]
Sent: Tuesday, November 14, 2017 7:57 AM
To: Joseph Myers <joseph@codesourcery.com>
Cc: Shalnov, Sergey <sergey.shalnov@intel.com>; gcc-patches@gcc.gnu.org; kirill.yukhin@gmail.com; Koval, Julia <julia.koval@intel.com>; Senkevich, Andrew <andrew.senkevich@intel.com>; Peryt, Sebastian <sebastian.peryt@intel.com>; Ivchenko, Alexander <alexander.ivchenko@intel.com>
Subject: Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
On Tue, Nov 14, 2017 at 12:14 AM, Joseph Myers <joseph@codesourcery.com> wrote:
> On Mon, 13 Nov 2017, Uros Bizjak wrote:
>
>> [BTW: --mprefer-avx128 should be marked RejectNegative from the
>> beginning; let's just assume nobody uses it in its (somehow weird)
>> negative "-mno-prefer-avx128" form.]
>
> It's used in that form in various testcases that otherwise fail when
> GCC is configured --with-arch= some CPU that defaults to -mprefer-avx128.
In this case, an even better choice would be:
Alias(mprefer-vector-width=, 128, none)
So, -mno-prefer-avx128 would just set the default back to none.
Uros.
[-- Attachment #2: 0004-Refactoring-options-mprefer-avx-128-256-into-one-mpr.patch --]
[-- Type: application/octet-stream, Size: 10239 bytes --]
From f6fa45a434334bcba763ab115591513f4f8a2dc5 Mon Sep 17 00:00:00 2001
From: Sergey Shalnov <Sergey.Shalnov@intel.com>
Date: Tue, 21 Nov 2017 09:03:54 +0300
Subject: [PATCH 1/1] Refactoring options mprefer-avx[128|256] into one
mprefer-vector-width
---
gcc/config/i386/i386-opts.h | 7 ++++++
gcc/config/i386/i386.c | 16 ++++++------
gcc/config/i386/i386.h | 5 ++++
gcc/config/i386/i386.opt | 29 ++++++++++++++++++----
gcc/doc/invoke.texi | 27 +++++++++++++-------
gcc/testsuite/g++.dg/ext/pr57362.C | 4 +--
gcc/testsuite/g++.dg/torture/pr81249.C | 2 +-
.../i386/avx512f-constant-float-return.c | 2 +-
gcc/testsuite/gcc.target/i386/avx512f-prefer.c | 2 +-
gcc/testsuite/gcc.target/i386/pr82460-2.c | 2 +-
10 files changed, 68 insertions(+), 28 deletions(-)
diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h
index 542cd0f..8c37a74 100644
--- a/gcc/config/i386/i386-opts.h
+++ b/gcc/config/i386/i386-opts.h
@@ -99,4 +99,11 @@ enum stack_protector_guard {
SSP_GLOBAL /* global canary */
};
+enum prefer_vector_width {
+ PVW_NONE,
+ PVW_AVX128,
+ PVW_AVX256,
+ PVW_AVX512
+};
+
#endif
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1775697..fb03d12 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -2847,15 +2847,13 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
{ "-mstv", MASK_STV },
{ "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD },
{ "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE },
- { "-mprefer-avx128", MASK_PREFER_AVX128 },
{ "-mcall-ms2sysv-xlogues", MASK_CALL_MS2SYSV_XLOGUES }
};
/* Additional flag options. */
static struct ix86_target_opts flag2_opts[] =
{
- { "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY },
- { "-mprefer-avx256", OPTION_MASK_PREFER_AVX256 },
+ { "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY }
};
const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (isa2_opts)
@@ -4686,16 +4684,18 @@ ix86_option_override_internal (bool main_args_p,
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
+
/* Enable 128-bit AVX instruction generation
for the auto-vectorizer. */
if (TARGET_AVX128_OPTIMAL
- && !(opts_set->x_target_flags & MASK_PREFER_AVX128))
- opts->x_target_flags |= MASK_PREFER_AVX128;
- /* Use 256-bit AVX instructions instead of 512-bit AVX instructions
+ && (opts_set->x_prefer_vector_width_type == PVW_NONE))
+ opts->x_prefer_vector_width_type = PVW_AVX128;
+
+ /* Use 256-bit AVX instruction generation
in the auto-vectorizer. */
if (ix86_tune_features[X86_TUNE_AVX256_OPTIMAL]
- && !(opts_set->x_ix86_target_flags & OPTION_MASK_PREFER_AVX256))
- opts->x_ix86_target_flags |= OPTION_MASK_PREFER_AVX256;
+ && (opts_set->x_prefer_vector_width_type == PVW_NONE))
+ opts->x_prefer_vector_width_type = PVW_AVX256;
if (opts->x_ix86_recip_name)
{
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index bc601c8..6eadc03 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2678,6 +2678,11 @@ extern void debug_dispatch_window (int);
#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
+/* Use 128-bit AVX instructions in the auto-vectorizer. */
+#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
+/* Use 256-bit AVX instructions in the auto-vectorizer. */
+#define TARGET_PREFER_AVX256 (prefer_vector_width_type == PVW_AVX256)
+
#define IX86_HLE_ACQUIRE (1 << 16)
#define IX86_HLE_RELEASE (1 << 17)
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 0fb4698..1827a0c 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -182,6 +182,10 @@ int x_ix86_tune_no_default
TargetSave
enum ix86_veclibabi x_ix86_veclibabi_type
+;; -mprefer-vector-width=
+TargetSave
+enum prefer_vector_width x_prefer_vector_width_type
+
;; x86 options
m128bit-long-double
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
@@ -588,12 +592,27 @@ Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
or znver1 and Haifa scheduling is selected.
mprefer-avx128
-Target Report Mask(PREFER_AVX128) Save
-Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
+Target Undocumented Alias(mprefer-vector-width=, 128, none)
+
+mprefer-vector-width=
+Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE)
+Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
+
+Enum
+Name(prefer_vector_width) Type(enum prefer_vector_width)
+Known preferred register vector length (to use with the -mprefer-vector-width= option)
+
+EnumValue
+Enum(prefer_vector_width) String(none) Value(PVW_NONE)
+
+EnumValue
+Enum(prefer_vector_width) String(128) Value(PVW_AVX128)
-mprefer-avx256
-Target Report Mask(PREFER_AVX256) Var(ix86_target_flags) Save
-Use 256-bit AVX instructions instead of 512-bit AVX instructions in the auto-vectorizer.
+EnumValue
+Enum(prefer_vector_width) String(256) Value(PVW_AVX256)
+
+EnumValue
+Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
;; ISA support
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index e18fa54..b483710 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1196,7 +1196,7 @@ See RS/6000 and PowerPC Options.
-mincoming-stack-boundary=@var{num} @gol
-mcld -mcx16 -msahf -mmovbe -mcrc32 @gol
-mrecip -mrecip=@var{opt} @gol
--mvzeroupper -mprefer-avx128 -mprefer-avx256 @gol
+-mvzeroupper -mprefer-vector-width=@var{opt} @gol
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -mavx512vl @gol
-mavx512bw -mavx512dq -mavx512ifma -mavx512vbmi -msha -maes @gol
@@ -26088,15 +26088,24 @@ before a transfer of control flow out of the function to minimize
the AVX to SSE transition penalty as well as remove unnecessary @code{zeroupper}
intrinsics.
-@item -mprefer-avx128
-@opindex mprefer-avx128
-This option instructs GCC to use 128-bit AVX instructions instead of
-256-bit AVX instructions in the auto-vectorizer.
+@item -mprefer-vector-width=@var{opt}
+@opindex mprefer-vector-width
+This option instructs GCC to use @var{opt}-bit vector width in instructions
+instead of default on the selected platform.
-@item -mprefer-avx256
-@opindex mprefer-avx256
-This option instructs GCC to use 256-bit AVX instructions instead of
-512-bit AVX instructions in the auto-vectorizer.
+@table @samp
+@item none
+No extra limitations applied to GCC other than defined by the selected platform.
+
+@item 128
+Prefer 128-bit vector width for instructions.
+
+@item 256
+Prefer 256-bit vector width for instructions.
+
+@item 512
+Prefer 512-bit vector width for instructions.
+@end table
@item -mcx16
@opindex mcx16
diff --git a/gcc/testsuite/g++.dg/ext/pr57362.C b/gcc/testsuite/g++.dg/ext/pr57362.C
index 3613b63..c9b3119 100644
--- a/gcc/testsuite/g++.dg/ext/pr57362.C
+++ b/gcc/testsuite/g++.dg/ext/pr57362.C
@@ -79,9 +79,9 @@ __attribute__((target("vzeroupper")))
int foo(void) { return 1; }
__attribute__((target("dispatch-scheduler")))
int foo(void) { return 1; }
-__attribute__((target("prefer-avx128")))
+__attribute__((target("prefer-vector-width=128")))
int foo(void) { return 1; }
-__attribute__((target("prefer-avx256")))
+__attribute__((target("prefer-vector-width=256")))
int foo(void) { return 1; }
__attribute__((target("32")))
int foo(void) { return 1; }
diff --git a/gcc/testsuite/g++.dg/torture/pr81249.C b/gcc/testsuite/g++.dg/torture/pr81249.C
index 7bf617b..5af319d 100644
--- a/gcc/testsuite/g++.dg/torture/pr81249.C
+++ b/gcc/testsuite/g++.dg/torture/pr81249.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-mavx2 -mprefer-avx128" { target x86_64-*-* i?86-*-* } } */
+/* { dg-additional-options "-mavx2 -mprefer-vector-width=128" { target x86_64-*-* i?86-*-* } } */
typedef struct rtx_def *rtx;
union rtunion {
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
index 153cf69..ed0becc 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-constant-float-return.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
float
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-prefer.c b/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
index defe51e..a74ce07 100644
--- a/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
+++ b/gcc/testsuite/gcc.target/i386/avx512f-prefer.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
/* { dg-final { scan-assembler "vmulpd" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr82460-2.c b/gcc/testsuite/gcc.target/i386/pr82460-2.c
index 4d96521..4a45bee 100644
--- a/gcc/testsuite/gcc.target/i386/pr82460-2.c
+++ b/gcc/testsuite/gcc.target/i386/pr82460-2.c
@@ -1,6 +1,6 @@
/* PR target/82460 */
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mno-prefer-avx256" } */
+/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mprefer-vector-width=none" } */
/* We want to reuse the permutation mask in the loop, so use vpermt2b rather
than vpermi2b. */
/* { dg-final { scan-assembler-not {\mvpermi2b\M} } } */
--
1.8.3.1
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-21 16:07 ` Shalnov, Sergey
@ 2017-11-21 17:19 ` Uros Bizjak
2017-11-21 17:29 ` Shalnov, Sergey
0 siblings, 1 reply; 10+ messages in thread
From: Uros Bizjak @ 2017-11-21 17:19 UTC (permalink / raw)
To: Shalnov, Sergey
Cc: gcc-patches, kirill.yukhin, Koval, Julia, Senkevich, Andrew,
Peryt, Sebastian, Ivchenko, Alexander, Joseph Myers
On Tue, Nov 21, 2017 at 4:50 PM, Shalnov, Sergey
<sergey.shalnov@intel.com> wrote:
> Uros,
> I did new patch with all comments addressed as proposed.
> 1. old option -mprefer-avx128 is Alias(mprefer-vector-width=, 128, none)
> 2. Simplified default initialization (as Bernhard proposed)
> 3. Fixed documentation (proposed by Sandra)
> 4. Several tests are changed to use new style of the option but many leaved with -mprefer-avx128 (one test with new style -mprefer-vector-width=128)
>
>
> 2017-11-21 Sergey Shalnov <Sergey.Shalnov@intel.com>
>
> gcc/
> * config/i386/i386-opts.h (enum prefer_vector_width): Added new enum
> for the new option -mprefer-vector-width=[none|128|256|512].
> * config/i386/i386.c (ix86_target_string): remove old style options
> -mprefer-avx256 and make -mprefer-avx128 as alias.
> (ix86_option_override_internal): Apply defaults for the
> -mprefer-vector-width=[128|256] option.
> * config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256):
> Implement macros to work with -mprefer-vector-width=.
> * config/i386/i386.opt: Implemented option
> -mprefer-vector-width=[none|128|256|512].
> * doc/invoke.texi: Documentation for
> -mprefer-vector-width=[none|128|256|512].
>
> gcc/testsuite/
> * g++.dg/ext/pr57362.C (__attribute__): Apply new option syntax.
> * g++.dg/torture/pr81249.C: Ditto.
> * gcc.target/i386/avx512f-constant-float-return.c: Ditto.
> * gcc.target/i386/avx512f-prefer.c: Ditto.
> * gcc.target/i386/pr82460-2.c: Ditto.
>
> Please merge this patch if you think it is acceptable.
> Thank you
> Sergey
mprefer-avx128
-Target Report Mask(PREFER_AVX128) Save
-Use 128-bit AVX instructions instead of 256-bit AVX instructions in
the auto-vectorizer.
+Target Undocumented Alias(mprefer-vector-width=, 128, none)
For compatibility, I'd rather leave this option documented with:
+Target Alias(mprefer-vector-width=, 128, 256)
This would mean that in addition to -mprefer-avx128 switching to
128-bit AVX, -mno-prefer-avx128 would switch to 256-bit AVX, as
documented for the option.
The patch is OK, and If you agree, I can commit the patch with the above change.
Thanks,
Uros.
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-21 17:19 ` Uros Bizjak
@ 2017-11-21 17:29 ` Shalnov, Sergey
2017-11-21 20:04 ` Uros Bizjak
0 siblings, 1 reply; 10+ messages in thread
From: Shalnov, Sergey @ 2017-11-21 17:29 UTC (permalink / raw)
To: Uros Bizjak
Cc: gcc-patches, kirill.yukhin, Koval, Julia, Senkevich, Andrew,
Peryt, Sebastian, Ivchenko, Alexander, Joseph Myers
Uros,
Yes, please. Thank you for your proposals and comments.
Please commit as you proposed.
Sergey
-----Original Message-----
From: Uros Bizjak [mailto:ubizjak@gmail.com]
Sent: Tuesday, November 21, 2017 6:13 PM
To: Shalnov, Sergey <sergey.shalnov@intel.com>
Cc: gcc-patches@gcc.gnu.org; kirill.yukhin@gmail.com; Koval, Julia <julia.koval@intel.com>; Senkevich, Andrew <andrew.senkevich@intel.com>; Peryt, Sebastian <sebastian.peryt@intel.com>; Ivchenko, Alexander <alexander.ivchenko@intel.com>; Joseph Myers <joseph@codesourcery.com>
Subject: Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
On Tue, Nov 21, 2017 at 4:50 PM, Shalnov, Sergey <sergey.shalnov@intel.com> wrote:
> Uros,
> I did new patch with all comments addressed as proposed.
> 1. old option -mprefer-avx128 is Alias(mprefer-vector-width=, 128,
> none) 2. Simplified default initialization (as Bernhard proposed) 3.
> Fixed documentation (proposed by Sandra) 4. Several tests are changed
> to use new style of the option but many leaved with -mprefer-avx128
> (one test with new style -mprefer-vector-width=128)
>
>
> 2017-11-21 Sergey Shalnov <Sergey.Shalnov@intel.com>
>
> gcc/
> * config/i386/i386-opts.h (enum prefer_vector_width): Added new enum
> for the new option -mprefer-vector-width=[none|128|256|512].
> * config/i386/i386.c (ix86_target_string): remove old style options
> -mprefer-avx256 and make -mprefer-avx128 as alias.
> (ix86_option_override_internal): Apply defaults for the
> -mprefer-vector-width=[128|256] option.
> * config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256):
> Implement macros to work with -mprefer-vector-width=.
> * config/i386/i386.opt: Implemented option
> -mprefer-vector-width=[none|128|256|512].
> * doc/invoke.texi: Documentation for
> -mprefer-vector-width=[none|128|256|512].
>
> gcc/testsuite/
> * g++.dg/ext/pr57362.C (__attribute__): Apply new option syntax.
> * g++.dg/torture/pr81249.C: Ditto.
> * gcc.target/i386/avx512f-constant-float-return.c: Ditto.
> * gcc.target/i386/avx512f-prefer.c: Ditto.
> * gcc.target/i386/pr82460-2.c: Ditto.
>
> Please merge this patch if you think it is acceptable.
> Thank you
> Sergey
mprefer-avx128
-Target Report Mask(PREFER_AVX128) Save
-Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
+Target Undocumented Alias(mprefer-vector-width=, 128, none)
For compatibility, I'd rather leave this option documented with:
+Target Alias(mprefer-vector-width=, 128, 256)
This would mean that in addition to -mprefer-avx128 switching to 128-bit AVX, -mno-prefer-avx128 would switch to 256-bit AVX, as documented for the option.
The patch is OK, and If you agree, I can commit the patch with the above change.
Thanks,
Uros.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-21 17:29 ` Shalnov, Sergey
@ 2017-11-21 20:04 ` Uros Bizjak
0 siblings, 0 replies; 10+ messages in thread
From: Uros Bizjak @ 2017-11-21 20:04 UTC (permalink / raw)
To: Shalnov, Sergey
Cc: gcc-patches, kirill.yukhin, Koval, Julia, Senkevich, Andrew,
Peryt, Sebastian, Ivchenko, Alexander, Joseph Myers
[-- Attachment #1: Type: text/plain, Size: 3212 bytes --]
I have committed the attached patch.
Uros.
On Tue, Nov 21, 2017 at 6:18 PM, Shalnov, Sergey
<sergey.shalnov@intel.com> wrote:
> Uros,
> Yes, please. Thank you for your proposals and comments.
> Please commit as you proposed.
> Sergey
>
> -----Original Message-----
> From: Uros Bizjak [mailto:ubizjak@gmail.com]
> Sent: Tuesday, November 21, 2017 6:13 PM
> To: Shalnov, Sergey <sergey.shalnov@intel.com>
> Cc: gcc-patches@gcc.gnu.org; kirill.yukhin@gmail.com; Koval, Julia <julia.koval@intel.com>; Senkevich, Andrew <andrew.senkevich@intel.com>; Peryt, Sebastian <sebastian.peryt@intel.com>; Ivchenko, Alexander <alexander.ivchenko@intel.com>; Joseph Myers <joseph@codesourcery.com>
> Subject: Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
>
> On Tue, Nov 21, 2017 at 4:50 PM, Shalnov, Sergey <sergey.shalnov@intel.com> wrote:
>> Uros,
>> I did new patch with all comments addressed as proposed.
>> 1. old option -mprefer-avx128 is Alias(mprefer-vector-width=, 128,
>> none) 2. Simplified default initialization (as Bernhard proposed) 3.
>> Fixed documentation (proposed by Sandra) 4. Several tests are changed
>> to use new style of the option but many leaved with -mprefer-avx128
>> (one test with new style -mprefer-vector-width=128)
>>
>>
>> 2017-11-21 Sergey Shalnov <Sergey.Shalnov@intel.com>
>>
>> gcc/
>> * config/i386/i386-opts.h (enum prefer_vector_width): Added new enum
>> for the new option -mprefer-vector-width=[none|128|256|512].
>> * config/i386/i386.c (ix86_target_string): remove old style options
>> -mprefer-avx256 and make -mprefer-avx128 as alias.
>> (ix86_option_override_internal): Apply defaults for the
>> -mprefer-vector-width=[128|256] option.
>> * config/i386/i386.h (TARGET_PREFER_AVX128, TARGET_PREFER_AVX256):
>> Implement macros to work with -mprefer-vector-width=.
>> * config/i386/i386.opt: Implemented option
>> -mprefer-vector-width=[none|128|256|512].
>> * doc/invoke.texi: Documentation for
>> -mprefer-vector-width=[none|128|256|512].
>>
>> gcc/testsuite/
>> * g++.dg/ext/pr57362.C (__attribute__): Apply new option syntax.
>> * g++.dg/torture/pr81249.C: Ditto.
>> * gcc.target/i386/avx512f-constant-float-return.c: Ditto.
>> * gcc.target/i386/avx512f-prefer.c: Ditto.
>> * gcc.target/i386/pr82460-2.c: Ditto.
>>
>> Please merge this patch if you think it is acceptable.
>> Thank you
>> Sergey
>
> mprefer-avx128
> -Target Report Mask(PREFER_AVX128) Save
> -Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
> +Target Undocumented Alias(mprefer-vector-width=, 128, none)
>
> For compatibility, I'd rather leave this option documented with:
>
> +Target Alias(mprefer-vector-width=, 128, 256)
>
> This would mean that in addition to -mprefer-avx128 switching to 128-bit AVX, -mno-prefer-avx128 would switch to 256-bit AVX, as documented for the option.
>
> The patch is OK, and If you agree, I can commit the patch with the above change.
>
> Thanks,
> Uros.
[-- Attachment #2: p.diff.txt --]
[-- Type: text/plain, Size: 8814 bytes --]
Index: config/i386/i386-opts.h
===================================================================
--- config/i386/i386-opts.h (revision 255016)
+++ config/i386/i386-opts.h (working copy)
@@ -99,4 +99,11 @@ enum stack_protector_guard {
SSP_GLOBAL /* global canary */
};
+enum prefer_vector_width {
+ PVW_NONE,
+ PVW_AVX128,
+ PVW_AVX256,
+ PVW_AVX512
+};
+
#endif
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c (revision 255016)
+++ config/i386/i386.c (working copy)
@@ -2847,7 +2847,6 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_I
{ "-mstv", MASK_STV },
{ "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD },
{ "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE },
- { "-mprefer-avx128", MASK_PREFER_AVX128 },
{ "-mcall-ms2sysv-xlogues", MASK_CALL_MS2SYSV_XLOGUES }
};
@@ -2854,8 +2853,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_I
/* Additional flag options. */
static struct ix86_target_opts flag2_opts[] =
{
- { "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY },
- { "-mprefer-avx256", OPTION_MASK_PREFER_AVX256 },
+ { "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY }
};
const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (isa2_opts)
@@ -4686,16 +4684,18 @@ ix86_option_override_internal (bool main_args_p,
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
+
/* Enable 128-bit AVX instruction generation
for the auto-vectorizer. */
if (TARGET_AVX128_OPTIMAL
- && !(opts_set->x_target_flags & MASK_PREFER_AVX128))
- opts->x_target_flags |= MASK_PREFER_AVX128;
- /* Use 256-bit AVX instructions instead of 512-bit AVX instructions
+ && (opts_set->x_prefer_vector_width_type == PVW_NONE))
+ opts->x_prefer_vector_width_type = PVW_AVX128;
+
+ /* Use 256-bit AVX instruction generation
in the auto-vectorizer. */
if (ix86_tune_features[X86_TUNE_AVX256_OPTIMAL]
- && !(opts_set->x_ix86_target_flags & OPTION_MASK_PREFER_AVX256))
- opts->x_ix86_target_flags |= OPTION_MASK_PREFER_AVX256;
+ && (opts_set->x_prefer_vector_width_type == PVW_NONE))
+ opts->x_prefer_vector_width_type = PVW_AVX256;
if (opts->x_ix86_recip_name)
{
Index: config/i386/i386.h
===================================================================
--- config/i386/i386.h (revision 255016)
+++ config/i386/i386.h (working copy)
@@ -2678,6 +2678,11 @@ extern void debug_dispatch_window (int);
#define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0)
#define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0)
+/* Use 128-bit AVX instructions in the auto-vectorizer. */
+#define TARGET_PREFER_AVX128 (prefer_vector_width_type == PVW_AVX128)
+/* Use 256-bit AVX instructions in the auto-vectorizer. */
+#define TARGET_PREFER_AVX256 (prefer_vector_width_type == PVW_AVX256)
+
#define IX86_HLE_ACQUIRE (1 << 16)
#define IX86_HLE_RELEASE (1 << 17)
Index: config/i386/i386.opt
===================================================================
--- config/i386/i386.opt (revision 255016)
+++ config/i386/i386.opt (working copy)
@@ -182,6 +182,10 @@ int x_ix86_tune_no_default
TargetSave
enum ix86_veclibabi x_ix86_veclibabi_type
+;; -mprefer-vector-width=
+TargetSave
+enum prefer_vector_width x_prefer_vector_width_type
+
;; x86 options
m128bit-long-double
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save
@@ -588,13 +592,29 @@ Do dispatch scheduling if processor is bdver1, bdv
or znver1 and Haifa scheduling is selected.
mprefer-avx128
-Target Report Mask(PREFER_AVX128) Save
+Target Alias(mprefer-vector-width=, 128, 256)
Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
-mprefer-avx256
-Target Report Mask(PREFER_AVX256) Var(ix86_target_flags) Save
-Use 256-bit AVX instructions instead of 512-bit AVX instructions in the auto-vectorizer.
+mprefer-vector-width=
+Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE)
+Use given register vector width instructions instead of maximum register width in the auto-vectorizer.
+Enum
+Name(prefer_vector_width) Type(enum prefer_vector_width)
+Known preferred register vector length (to use with the -mprefer-vector-width= option)
+
+EnumValue
+Enum(prefer_vector_width) String(none) Value(PVW_NONE)
+
+EnumValue
+Enum(prefer_vector_width) String(128) Value(PVW_AVX128)
+
+EnumValue
+Enum(prefer_vector_width) String(256) Value(PVW_AVX256)
+
+EnumValue
+Enum(prefer_vector_width) String(512) Value(PVW_AVX512)
+
;; ISA support
m32
Index: doc/invoke.texi
===================================================================
--- doc/invoke.texi (revision 255016)
+++ doc/invoke.texi (working copy)
@@ -1196,7 +1196,7 @@ See RS/6000 and PowerPC Options.
-mincoming-stack-boundary=@var{num} @gol
-mcld -mcx16 -msahf -mmovbe -mcrc32 @gol
-mrecip -mrecip=@var{opt} @gol
--mvzeroupper -mprefer-avx128 -mprefer-avx256 @gol
+-mvzeroupper -mprefer-avx128 -mprefer-vector-width=@var{opt} @gol
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -mavx512vl @gol
-mavx512bw -mavx512dq -mavx512ifma -mavx512vbmi -msha -maes @gol
@@ -26093,11 +26093,25 @@ intrinsics.
This option instructs GCC to use 128-bit AVX instructions instead of
256-bit AVX instructions in the auto-vectorizer.
-@item -mprefer-avx256
-@opindex mprefer-avx256
-This option instructs GCC to use 256-bit AVX instructions instead of
-512-bit AVX instructions in the auto-vectorizer.
+@item -mprefer-vector-width=@var{opt}
+@opindex mprefer-vector-width
+This option instructs GCC to use @var{opt}-bit vector width in instructions
+instead of default on the selected platform.
+@table @samp
+@item none
+No extra limitations applied to GCC other than defined by the selected platform.
+
+@item 128
+Prefer 128-bit vector width for instructions.
+
+@item 256
+Prefer 256-bit vector width for instructions.
+
+@item 512
+Prefer 512-bit vector width for instructions.
+@end table
+
@item -mcx16
@opindex mcx16
This option enables GCC to generate @code{CMPXCHG16B} instructions in 64-bit
Index: testsuite/g++.dg/ext/pr57362.C
===================================================================
--- testsuite/g++.dg/ext/pr57362.C (revision 255016)
+++ testsuite/g++.dg/ext/pr57362.C (working copy)
@@ -81,8 +81,10 @@ __attribute__((target("dispatch-scheduler")))
int foo(void) { return 1; }
__attribute__((target("prefer-avx128")))
int foo(void) { return 1; }
-__attribute__((target("prefer-avx256")))
+__attribute__((target("prefer-vector-width=128")))
int foo(void) { return 1; }
+__attribute__((target("prefer-vector-width=256")))
+int foo(void) { return 1; }
__attribute__((target("32")))
int foo(void) { return 1; }
__attribute__((target("64")))
Index: testsuite/gcc.target/i386/avx512f-constant-float-return.c
===================================================================
--- testsuite/gcc.target/i386/avx512f-constant-float-return.c (revision 255016)
+++ testsuite/gcc.target/i386/avx512f-constant-float-return.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
float
Index: testsuite/gcc.target/i386/avx512f-prefer.c
===================================================================
--- testsuite/gcc.target/i386/avx512f-prefer.c (revision 255016)
+++ testsuite/gcc.target/i386/avx512f-prefer.c (working copy)
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
+/* { dg-options "-O3 -march=skylake-avx512 -mprefer-vector-width=256" } */
/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
/* { dg-final { scan-assembler "vmulpd" } } */
Index: testsuite/gcc.target/i386/pr82460-2.c
===================================================================
--- testsuite/gcc.target/i386/pr82460-2.c (revision 255016)
+++ testsuite/gcc.target/i386/pr82460-2.c (working copy)
@@ -1,6 +1,6 @@
/* PR target/82460 */
/* { dg-do compile } */
-/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mno-prefer-avx256" } */
+/* { dg-options "-O2 -ftree-vectorize -mavx512vbmi -mprefer-vector-width=none" } */
/* We want to reuse the permutation mask in the loop, so use vpermt2b rather
than vpermi2b. */
/* { dg-final { scan-assembler-not {\mvpermi2b\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512]
2017-11-13 17:37 [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512] Shalnov, Sergey
2017-11-13 20:23 ` Uros Bizjak
@ 2017-11-14 19:38 ` Sandra Loosemore
1 sibling, 0 replies; 10+ messages in thread
From: Sandra Loosemore @ 2017-11-14 19:38 UTC (permalink / raw)
To: Shalnov, Sergey, 'gcc-patches@gcc.gnu.org'
Cc: 'kirill.yukhin@gmail.com', 'ubizjak@gmail.com',
Koval, Julia, Senkevich, Andrew, Peryt, Sebastian, Ivchenko,
Alexander
On 11/13/2017 10:25 AM, Shalnov, Sergey wrote:
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 4427328..bc9eb85 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -26087,15 +26087,24 @@ before a transfer of control flow out of the function to minimize
> the AVX to SSE transition penalty as well as remove unnecessary @code{zeroupper}
> intrinsics.
>
> -@item -mprefer-avx128
> -@opindex mprefer-avx128
> -This option instructs GCC to use 128-bit AVX instructions instead of
> -256-bit AVX instructions in the auto-vectorizer.
> +@item -mprefer-vector-width=@var{opt}
> +@opindex mprefer-vector-width
> +This option instructs GCC to use @var{opt}-bit vector width in instructions
> +instead of default on the selected platform.
>
> -@item -mprefer-avx256
> -@opindex mprefer-avx256
> -This option instructs GCC to use 256-bit AVX instructions instead of
> -512-bit AVX instructions in the auto-vectorizer.
> +@table @samp
> +@item none
> +No extra limitations applied to GCC over than defined by the selected platform.
> +
s/over than/other than/ ???
-Sandra
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2017-11-21 19:53 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-13 17:37 [PATCH, i386] Refactor -mprefer-avx[128|256] options into common -mprefer-vector-width=[none|128|256|512] Shalnov, Sergey
2017-11-13 20:23 ` Uros Bizjak
2017-11-13 20:32 ` Uros Bizjak
2017-11-13 23:41 ` Joseph Myers
2017-11-14 8:31 ` Uros Bizjak
2017-11-21 16:07 ` Shalnov, Sergey
2017-11-21 17:19 ` Uros Bizjak
2017-11-21 17:29 ` Shalnov, Sergey
2017-11-21 20:04 ` Uros Bizjak
2017-11-14 19:38 ` Sandra Loosemore
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