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Date: Wed, 19 Oct 2011 14:38:00 -0000
Message-ID: <CAFULd4Yf478LBLh+NgyVqvHsPVAFM=uaQ1e2jbZ0PLgT2Ny4-Q@mail.gmail.com>
Subject: Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
From: Uros Bizjak <ubizjak@gmail.com>
To: Kirill Yukhin <kirill.yukhin@gmail.com>
Cc: "H.J. Lu" <hjl.tools@gmail.com>, gcc-patches List <gcc-patches@gcc.gnu.org>
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On Wed, Oct 19, 2011 at 3:07 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wr=
ote:

> Here is (almost obvous) patch, which fixes PR50766.
>
> ChangeLog =A0entry:
> 2011-10-19 =A0Kirill Yukhin =A0<kirill.yukhin@intel.com>
>
> =A0 =A0 =A0 =A0* config/i386/i386.md (bmi_bextr_<mode>): Update register/
> =A0 =A0 =A0 =A0memory operand order.
> =A0 =A0 =A0 =A0(bmi2_bzhi_<mode>3): Ditto.
> =A0 =A0 =A0 =A0(bmi2_pdep_<mode>3): Ditto.
> =A0 =A0 =A0 =A0(bmi2_pext_<mode>3): Ditto.
>
> Bootstrapped, test (from bug) passing.
>
> Could you please have a look?

Please also add the testcase from the PR. You can use  { dg-do
assemble }, but you have to check for BMI2 effective target support.

BTW: I can't find BMI2 instruction reference documentation, so I'm
just rubberstamping the patch as obvious.

So, OK with the testcase.

Thanks,
Uros.