From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x835.google.com (mail-qt1-x835.google.com [IPv6:2607:f8b0:4864:20::835]) by sourceware.org (Postfix) with ESMTPS id E3058385AC3E for ; Wed, 17 Nov 2021 09:09:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E3058385AC3E Received: by mail-qt1-x835.google.com with SMTP id t11so1981245qtw.3 for ; Wed, 17 Nov 2021 01:09:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=JmzSLPs7RnOEzMNVDjizUVUE3sFTSbX118M9VipLrYw=; b=YHf54ZEhepPUPy2FgJHeaUJLyYdMcnoBHfY5t2Loj3Q42QkkpIDm9MLiBeSXwj6btW gZBO1Z+cArXfMjpOn7H3/6GXZagmT2ITim+CXVIyj0CF1QQM5qaXanhyjHvz5gRBjErE i8u/5QZaXED9kgq/j/vlVLm3ES4mDVdTQDscneSXwo8qUKI9HKdYt6UWGWEXzQIZkuQT rReNlgt/yDksqbQA+1oi5cqWmuiTu6K/YFBDQ8UG8Gl0j8i2ttXcvjivNJo2QV6LV67g OYWWnfIstRYD/d1p5ZnD+k3ggMkISSKzG0RloGAaxkoGMCWGJO8TuaazmUX+cI+qoqIB wi7Q== X-Gm-Message-State: AOAM530Rqq5hM1fVykDDHfqNl4O21OxEnv4nHjUufjApijoT5TffCAgo TDQOu37v+gSxcweb64v4jBZIoBPcrwH0+MKWSGU= X-Google-Smtp-Source: ABdhPJxE5SvUOq9aRF0MijYoBHQaWjjIhYQh10qR98+7bEIYSEf0JrCkjPwRaNRWp1nuBztUpt+2EdDZuPYIHahHjog= X-Received: by 2002:a05:622a:1745:: with SMTP id l5mr14907136qtk.169.1637140199469; Wed, 17 Nov 2021 01:09:59 -0800 (PST) MIME-Version: 1.0 References: <20211116185055.3867815-1-hjl.tools@gmail.com> In-Reply-To: <20211116185055.3867815-1-hjl.tools@gmail.com> From: Uros Bizjak Date: Wed, 17 Nov 2021 10:09:47 +0100 Message-ID: Subject: Re: [PATCH] x86: Add -mindirect-branch-cs-prefix To: "H.J. Lu" Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Nov 2021 09:10:02 -0000 On Tue, Nov 16, 2021 at 7:51 PM H.J. Lu via Gcc-patches wrote: > > Add -mindirect-branch-cs-prefix to add CS prefix to call and jmp to thunk > via r8-r15 registers when converting indirect call and jump to increase > the instruction length to 6, allowing the non-thunk form to be inlined. > > gcc/ > > PR target/102952 > * config/i386/i386.c (ix86_output_jmp_thunk_or_indirect): Emit > CS prefix for -mindirect-branch-cs-prefix. > (ix86_output_indirect_branch_via_reg): Likewise. > * config/i386/i386.opt: Add -mindirect-branch-cs-prefix. > * doc/invoke.texi: Document -mindirect-branch-cs-prefix. > > gcc/testsuite/ > > PR target/102952 > * gcc.target/i386/indirect-thunk-cs-prefix-1.c: New test. > * gcc.target/i386/indirect-thunk-cs-prefix-2.c: Likewise. > --- > gcc/config/i386/i386.c | 6 ++++++ > gcc/config/i386/i386.opt | 4 ++++ > gcc/doc/invoke.texi | 8 +++++++- > .../gcc.target/i386/indirect-thunk-cs-prefix-1.c | 14 ++++++++++++++ > .../gcc.target/i386/indirect-thunk-cs-prefix-2.c | 15 +++++++++++++++ > 5 files changed, 46 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-2.c > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > index 7e9b7bc347f..0a902d66321 100644 > --- a/gcc/config/i386/i386.c > +++ b/gcc/config/i386/i386.c > @@ -15983,6 +15983,9 @@ ix86_output_jmp_thunk_or_indirect (const char *thunk_name, const int regno) > { > if (thunk_name != NULL) > { > + if (regno >= FIRST_REX_INT_REG REX_INT_REGNO_P > + && ix86_indirect_branch_cs_prefix) > + fprintf (asm_out_file, "\tcs\n"); > fprintf (asm_out_file, "\tjmp\t"); > assemble_name (asm_out_file, thunk_name); > putc ('\n', asm_out_file); > @@ -16036,6 +16039,9 @@ ix86_output_indirect_branch_via_reg (rtx call_op, bool sibcall_p) > { > if (thunk_name != NULL) > { > + if (regno >= FIRST_REX_INT_REG REX_INT_REGNO_P > + && ix86_indirect_branch_cs_prefix) > + fprintf (asm_out_file, "\tcs\n"); > fprintf (asm_out_file, "\tcall\t"); > assemble_name (asm_out_file, thunk_name); > putc ('\n', asm_out_file); > diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt > index 8d499a5a4df..c5452c49597 100644 > --- a/gcc/config/i386/i386.opt > +++ b/gcc/config/i386/i386.opt > @@ -1076,6 +1076,10 @@ Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline) > EnumValue > Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) > > +mindirect-branch-cs-prefix > +Target Var(ix86_indirect_branch_cs_prefix) Init(0) > +Add CS prefix to call and jmp to thunk when converting indirect call and jump. This is not what the function really does. It adds cs to REX prefixed regs. > + > mindirect-branch-register > Target Var(ix86_indirect_branch_register) Init(0) > Force indirect call and jump via register. > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index f3b4b467765..c992a7152f5 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -1425,7 +1425,8 @@ See RS/6000 and PowerPC Options. > -mstack-protector-guard-symbol=@var{symbol} @gol > -mgeneral-regs-only -mcall-ms2sysv-xlogues -mrelax-cmpxchg-loop @gol > -mindirect-branch=@var{choice} -mfunction-return=@var{choice} @gol > --mindirect-branch-register -mharden-sls=@var{choice} -mneeded} > +-mindirect-branch-register -mharden-sls=@var{choice} @gol > +-mindirect-branch-cs-prefix -mneeded} > > @emph{x86 Windows Options} > @gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll @gol > @@ -32390,6 +32391,11 @@ hardening. @samp{return} enables SLS hardening for function return. > @samp{indirect-branch} enables SLS hardening for indirect branch. > @samp{all} enables all SLS hardening. > > +@item -mindirect-branch-cs-prefix > +@opindex mindirect-branch-cs-prefix > +Add CS prefix to call and jmp to thunk via r8-r15 registers when > +converting indirect call and jump. > + > @end table > > These @samp{-m} switches are supported in addition to the above > diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-1.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-1.c > new file mode 100644 > index 00000000000..db2f3416823 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-1.c > @@ -0,0 +1,14 @@ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-O2 -ffixed-rax -ffixed-rbx -ffixed-rcx -ffixed-rdx -ffixed-rdi -ffixed-rsi -mindirect-branch-cs-prefix -mindirect-branch=thunk-extern" } */ > +/* { dg-additional-options "-fno-pic" { target { ! *-*-darwin* } } } */ > + > +extern void (*fptr) (void); > + > +void > +foo (void) > +{ > + fptr (); > +} > + > +/* { dg-final { scan-assembler-times "jmp\[ \t\]+_?__x86_indirect_thunk_r\[0-9\]+" 1 } } */ > +/* { dg-final { scan-assembler-times "\tcs" 1 } } */ > diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-2.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-2.c > new file mode 100644 > index 00000000000..adfc39a49d4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/indirect-thunk-cs-prefix-2.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-O2 -ffixed-rax -ffixed-rbx -ffixed-rcx -ffixed-rdx -ffixed-rdi -ffixed-rsi -mindirect-branch-cs-prefix -mindirect-branch=thunk-extern" } */ > +/* { dg-additional-options "-fno-pic" { target { ! *-*-darwin* } } } */ > + > +extern void (*bar) (void); > + > +int > +foo (void) > +{ > + bar (); > + return 0; > +} > + > +/* { dg-final { scan-assembler-times "call\[ \t\]+_?__x86_indirect_thunk_r\[0-9\]+" 1 } } */ > +/* { dg-final { scan-assembler-times "\tcs" 1 } } */ > -- > 2.33.1 >