From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 29022 invoked by alias); 21 Jun 2016 18:22:48 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 29013 invoked by uid 89); 21 Jun 2016 18:22:47 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.4 required=5.0 tests=AWL,BAYES_50,FREEMAIL_FROM,KAM_ASCII_DIVIDERS,KAM_STOCKGEN,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=no version=3.3.2 spammy=ubizjakgmailcom, ubizjak@gmail.com, CONST, SYMBOL_REF X-HELO: mail-vk0-f51.google.com Received: from mail-vk0-f51.google.com (HELO mail-vk0-f51.google.com) (209.85.213.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 21 Jun 2016 18:22:37 +0000 Received: by mail-vk0-f51.google.com with SMTP id u64so31593678vkf.3 for ; Tue, 21 Jun 2016 11:22:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=D9LkF/jENkVBTSCOFa/bWKu00aRdxgZqpMpOKBIUMJY=; b=Cp1b0FHqn2ZdsAY53x8MYg18GBXY8XnRbq0flzOlBgVudWJRl/3w5quTb4nRKaJP/+ bzhrfQ8VQHgMve1eV1qvob0ve2ftEVSDf1v11zhsSpoZbzjCgH9oKKwQ8lOrzrw7FPSi aPepY+uqJ1rNOCboev76P5TqMdai3Qr2fj/t1xTFgTjQH/BLDOjCZLilxW43PrSPCVaO PKnGDN/r3H+s/3LsMoWI3owU1A9MFW8ziF5AC+aB4QaMHl7Y4Sd+KJT/zxXiY/FfoE0B 1NlA75GQ6cBp9i19LL5+9yzIq8JmSuyqJb3FdvWlauJdU6CesoswePRDV3xBW1T90vYM lsCg== X-Gm-Message-State: ALyK8tIX1ano9N200nIVpXNhUs0S/r5Kc+686VKz3NcjhMmOR4flNsuQrYEoKlqpxqucdpDPv96/plbDsF1xBw== X-Received: by 10.176.6.230 with SMTP id g93mr9809347uag.50.1466533354594; Tue, 21 Jun 2016 11:22:34 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.19.198 with HTTP; Tue, 21 Jun 2016 11:22:33 -0700 (PDT) In-Reply-To: References: <20160620170501.GA18281@intel.com> <87shw7d4nl.fsf@googlemail.com> From: Uros Bizjak Date: Tue, 21 Jun 2016 18:22:00 -0000 Message-ID: Subject: Re: [PATCH] x86-64: Load external function address via GOT slot To: "H.J. Lu" Cc: "gcc-patches@gcc.gnu.org" , Jakub Jelinek , Richard Sandiford Content-Type: multipart/mixed; boundary=94eb2c047bc8a7034f0535cde743 X-SW-Source: 2016-06/txt/msg01531.txt.bz2 --94eb2c047bc8a7034f0535cde743 Content-Type: text/plain; charset=UTF-8 Content-length: 4052 On Tue, Jun 21, 2016 at 2:40 PM, H.J. Lu wrote: > On Mon, Jun 20, 2016 at 12:46 PM, Richard Sandiford > wrote: >> Uros Bizjak writes: >>> On Mon, Jun 20, 2016 at 9:19 PM, H.J. Lu wrote: >>>> On Mon, Jun 20, 2016 at 12:13 PM, Uros Bizjak wrote: >>>>> On Mon, Jun 20, 2016 at 7:05 PM, H.J. Lu wrote: >>>>>> Hi, >>>>>> >>>>>> This patch implements the alternate code sequence recommended in >>>>>> >>>>>> https://groups.google.com/forum/#!topic/x86-64-abi/de5_KnLHxtI >>>>>> >>>>>> to load external function address via GOT slot with >>>>>> >>>>>> movq func@GOTPCREL(%rip), %rax >>>>>> >>>>>> so that linker won't create an PLT entry for extern function >>>>>> address. >>>>>> >>>>>> Tested on x86-64. OK for trunk? >>>>> >>>>>> + else if (ix86_force_load_from_GOT_p (op1)) >>>>>> + { >>>>>> + /* Load the external function address via the GOT slot to >>>>>> + avoid PLT. */ >>>>>> + op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op1), >>>>>> + (TARGET_64BIT >>>>>> + ? UNSPEC_GOTPCREL >>>>>> + : UNSPEC_GOT)); >>>>>> + op1 = gen_rtx_CONST (Pmode, op1); >>>>>> + op1 = gen_const_mem (Pmode, op1); >>>>>> + /* This symbol must be referenced via a load from the Global >>>>>> + Offset Table. */ >>>>>> + set_mem_alias_set (op1, ix86_GOT_alias_set ()); >>>>>> + op1 = convert_to_mode (mode, op1, 1); >>>>>> + op1 = force_reg (mode, op1); >>>>>> + emit_insn (gen_rtx_SET (op0, op1)); >>>>>> + /* Generate a CLOBBER so that there will be no REG_EQUAL note >>>>>> + on the last insn to prevent cse and fwprop from replacing >>>>>> + a GOT load with a constant. */ >>>>>> + rtx tmp = gen_reg_rtx (Pmode); >>>>>> + emit_clobber (tmp); >>>>>> + return; >>>>> >>>>> Jeff, is this the recommended way to prevent CSE, as far as RTL >>>>> infrastructure is concerned? I didn't find any example of this >>>>> approach with other targets. >>>>> >>>> >>>> FWIW, the similar approach is used in ix86_expand_vector_move_misalign, >>>> ix86_expand_convert_uns_didf_sse and ix86_expand_vector_init_general >>>> as well as other targets: >>>> >>>> frv/frv.c: emit_clobber (op0); >>>> frv/frv.c: emit_clobber (op1); >>>> im32c/m32c.c: /* emit_clobber (gen_rtx_REG (HImode, R0L_REGNO)); */ >>>> s390/s390.c: emit_clobber (addr); >>>> s390/s390.md: emit_clobber (reg0); >>>> s390/s390.md: emit_clobber (reg1); >>>> s390/s390.md: emit_clobber (reg0); >>>> s390/s390.md: emit_clobber (reg0); >>>> s390/s390.md: emit_clobber (reg1); >>> >>> These usages mark the whole register as being "clobbered" >>> (=undefined), before only a part of register is written, e.g.: >>> >>> emit_clobber (int_xmm); >>> emit_move_insn (gen_lowpart (DImode, int_xmm), input); >>> >>> They aren't used to prevent unwanted CSE. >> >> Since it's being called in the move expander, I thought the normal >> way of preventing the constant being rematerialised would be to reject >> it in the move define_insn predicates. >> >> FWIW, I agree that using a clobber for this is going to be fragile. >> > > Here is the patch without clobber. Tested on x86-64. OK for > trunk? No, your patch has multiple problems: 1. It won't work for e.g. &bar+1, since you have to legitimize the symbol in two places of ix86_expand_move. Also, why use TARGET_64BIT in + op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op1), + (TARGET_64BIT + ? UNSPEC_GOTPCREL + : UNSPEC_GOT)); when ix86_force_load_from_GOT_p rejects non-64bit targets? 2. New check should be added to ix86_legitimate_constant_p, not to predicates of move insn patterns. Unfortunately, we still have to change x86_64_immediate_operand in two places. I have attached my version of the patch. It handles all your testcases, plus &foo+1 case. Bootstrap is still running. Does the patch work for you? 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