From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x82b.google.com (mail-qt1-x82b.google.com [IPv6:2607:f8b0:4864:20::82b]) by sourceware.org (Postfix) with ESMTPS id 7C50D3857801 for ; Fri, 15 Oct 2021 14:41:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7C50D3857801 Received: by mail-qt1-x82b.google.com with SMTP id g17so718006qtk.8 for ; Fri, 15 Oct 2021 07:41:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=dZoVW5EUhjbx0wVN4UfCht4X/jmgQdQj1Qyv4jq7iB0=; b=G9LboGzskwvNc4SDVF7Sky7he9xfrDZYo+MaLyZrLByFrEMBBuM9lXe8uHfsoHpfzk 3CSdY9WUdilIByhRiBspvoujVxjGcYQCwpeVfUJP3sVd0L3TqzMHqfjaiTE4Fu5Rul8O JcoLECCyUGyJyGSuy3LGIqMWsyT8swhQY5WZRbIPm9NOY9pgNrsqOJidlLlqpc7YZywF JgBltjAu6KRJJc+hZYA4ScBy+DJoYXuJz7YK4b5mijwx+2eNRBQos1vzRRQIsINxuP7H O/zaXtC4N766l1gkRHvMxIREAge+FhCDTzIK0UrYEwbmPgn/wDK91He3mNgVIvIX7PMa oEGQ== X-Gm-Message-State: AOAM533lUYkuDRCFNxF157E+HDGIUB1COPBd7bCYv8truya7p38s+ZXo B2viykAJxumMBYpJXNbb13gMObJegVGHk8P3xgw= X-Google-Smtp-Source: ABdhPJz26b8M0o1DTdwnmIc+SysfQ4Ar9yppyKAjJC8SI237JpCujQKSXEwO0BkWUD9p6xxQr/rZY0GCuNngluQutpc= X-Received: by 2002:a05:622a:1494:: with SMTP id t20mr14129717qtx.282.1634308916069; Fri, 15 Oct 2021 07:41:56 -0700 (PDT) MIME-Version: 1.0 References: <002c01d7c1be$689d3840$39d7a8c0$@nextmovesoftware.com> In-Reply-To: <002c01d7c1be$689d3840$39d7a8c0$@nextmovesoftware.com> From: Uros Bizjak Date: Fri, 15 Oct 2021 16:41:44 +0200 Message-ID: Subject: Re: [PATCH] Allow early sets of SSE hard registers from standard_sse_constant_p To: Roger Sayle Cc: GCC Patches , "H.J. Lu" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Oct 2021 14:41:57 -0000 On Fri, Oct 15, 2021 at 2:15 PM Roger Sayle wrote: > > > My previous patch, which was intended to reduce the differences seen by > the combination of -march=cascadelake and -m32, has additionally found > some more instances where this combination behaves differently to regular > x86_64-pc-linux-gnu. The middle-end always, and backends usually, use > emit_move_insn to emit/expand move instructions allowing the backend > control over placing things in constant pools, adding REG_EQUAL notes, > and so on. Several of the AVX512 built-in expanders bypass this logic, > and instead generate moves directly using emit_insn(gen_rtx_SET (dst,src)). > > For example, i386-expand.c line 12004 contains: > for (i = 0; i < 8; i++) > emit_insn (gen_rtx_SET (xmm_regs[i], const0_rtx)); > > I suspect that in this case, loading of standard_sse_constant_p, my > change to require loading of likely spilled hard registers via a > pseudo is perhaps overly strict, so this patch/fix reallows these > immediate constants values to be loaded directly prior to reload. > > If anyone notices a (SPEC benchmark) performance regression with > this patch, I'll propose the more invasive fix to make more use of > emit_move_insn in the backend (and revert this fix), but all things > being equal it's best to leave things the way they previously were. > > This patch not only cures the regressions reported by Sunil's > tester, but in combination with the previous patch now has 7 fewer > unexpected failures in the testsuite with -m32 -march=cascadelake. > This patch has also been tested with "make bootstrap" and > "make -k check" on x86_64-pc-linux-gnu with no new failures. > > Ok for mainline? > Sorry again for the temporary inconvenience. > > > 2021-10-15 Roger Sayle > > gcc/ChangeLog > * config/i386/i386.c (ix86_hardreg_mov_ok): For vector modes, > allow standard_sse_constant_p immediate constants. LGTM. Thanks, Uros.