From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 28481 invoked by alias); 10 Feb 2012 17:56:07 -0000 Received: (qmail 28472 invoked by uid 22791); 10 Feb 2012 17:56:06 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-gx0-f175.google.com (HELO mail-gx0-f175.google.com) (209.85.161.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 10 Feb 2012 17:55:52 +0000 Received: by ggeq1 with SMTP id q1so1703114gge.20 for ; Fri, 10 Feb 2012 09:55:52 -0800 (PST) MIME-Version: 1.0 Received: by 10.236.127.145 with SMTP id d17mr10317203yhi.131.1328896552199; Fri, 10 Feb 2012 09:55:52 -0800 (PST) Received: by 10.146.241.19 with HTTP; Fri, 10 Feb 2012 09:55:52 -0800 (PST) In-Reply-To: <20120210174215.GA20285@intel.com> References: <20120210172506.GA19409@intel.com> <20120210174215.GA20285@intel.com> Date: Fri, 10 Feb 2012 18:01:00 -0000 Message-ID: Subject: Re: PATCH: PR target/52146: [x32] - Wrong code to access addresses 0x80000000 to 0xFFFFFFFF From: Uros Bizjak To: "H.J. Lu" Cc: gcc-patches@gcc.gnu.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2012-02/txt/msg00518.txt.bz2 On Fri, Feb 10, 2012 at 6:42 PM, H.J. Lu wrote: >> Since constant address in x32 is signed extended to 64bit, negative >> displacement without base nor index is out of range. =A0OK for trunk? >> > > Here is a different patch. > > H.J. > --- > gcc/ > > 2012-02-10 =A0Uros Bizjak =A0 > > =A0 =A0 =A0 =A0PR target/52146 > =A0 =A0 =A0 =A0* config/i386/i386.c (ix86_legitimate_address_p): Disallow > =A0 =A0 =A0 =A0negative constant address for x32. > > gcc/testsuite/ > > 2012-02-10 =A0H.J. Lu =A0 > > =A0 =A0 =A0 =A0PR target/52146 > =A0 =A0 =A0 =A0* gcc.target/i386/pr52146.c: New. > > diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c > index 009dd53..8f4e72e 100644 > --- a/gcc/config/i386/i386.c > +++ b/gcc/config/i386/i386.c > @@ -11932,6 +11932,13 @@ ix86_legitimate_address_p (enum machine_mode mod= e ATTRIBUTE_UNUSED, > =A0 rtx base, index, disp; > =A0 HOST_WIDE_INT scale; > > + =A0/* Since constant address in x32 is signed extended to 64bit, > + =A0 =A0 we have to prevent addresses from 0x80000000 to 0xffffffff. =A0= */ > + =A0if (TARGET_X32 > + =A0 =A0 =A0&& CONST_INT_P (addr) > + =A0 =A0 =A0&& val_signbit_known_set_p (SImode, INTVAL (addr))) As said in the PR, val_signbit_known_set_p is a bit overkill. Please use INTVAL (addr) < 0, it works as well. > +++ b/gcc/testsuite/gcc.target/i386/pr52146.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && { ! {= ia32 } } } } } */ we _are_ in x86 directory, so: /* { dg-do compile { target { ! { ia32 } } } } */ > +/* { dg-options "-O2 -mx32" } */ > + > +void test1() { > + =A0int* apic_tpr_addr =3D (int *)0xfee00080; > + =A0*apic_tpr_addr +=3D 4; > +} > +void test2() { > + =A0volatile int* apic_tpr_addr =3D (int *)0xfee00080; > + =A0*apic_tpr_addr =3D 0; No need for volatile. > +} > +void test3() { > + =A0volatile int* apic_tpr_addr =3D (int *)0x7fffffff; > + =A0*apic_tpr_addr =3D 0; > +} test2 is enough. No need to test what worked OK. > + > +/* { dg-final { scan-assembler-not "-18874240" } } */ Please also reformat the test to GNU coding standards. Patch is OK for 4.7 and 4.6 after bootstrap and regression test on x32 targ= et. Thanks, Uros.