From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yw1-x112b.google.com (mail-yw1-x112b.google.com [IPv6:2607:f8b0:4864:20::112b]) by sourceware.org (Postfix) with ESMTPS id C4D41385840C for ; Mon, 24 Oct 2022 09:45:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C4D41385840C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-yw1-x112b.google.com with SMTP id 00721157ae682-3691e040abaso80547077b3.9 for ; Mon, 24 Oct 2022 02:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=PiCbSvDy+x/EwjLy71gjmOESaOT1h8Gnz7CPTNwPKbU=; b=l4FWEjWSVQprtQ+ZhdeMB4g2Pw48PzcFOPbOYNEdKUQsGcIkQ8nTB4PmIqvuXVeo/F xvRG5Hq6XfF8G/8IrxlM8GQ9r+0idVqdEAWWfysh+wNyHzK3dowCO38u4uUY4HDrOzmH LtV9Peql8/Z5++3bPoi+VR3rmmsn++EWfj2oYlAcSDwzocUevjPTwcubBnAPxjULPOir JLRDtvM4zkYgBn/Jvv5oIHJcq48e/+vWGWjRNn/zIqg05XZ4vj1BOA7XnDHx+iE8ev+a NnqW4aWsJgaYkNilAQAOZA4omk2HTmTRGJ9ZlvQIWMf3CsvbJBNkoFSeUVNwXrId0X6F 6fog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=PiCbSvDy+x/EwjLy71gjmOESaOT1h8Gnz7CPTNwPKbU=; b=VeRb2l3i5EI7eW90CJLQ45M0ecNZ8u4zmHASStMZMjB6iY33DgewZmnQzKltE9PYtq W4s/FPeesJ0G7ph4NVp8sMRrCzjnnXvrj8AbgOZpaFr68PlLf7m0GtOHMi1tXOKPmEqB TbiO1G5qQY3k+c4NH/DFrSwMsw8LVRLkQnGuBGAiqrhO3xdr+Cig3+gAeYRdBD4Fts6y GKbcNrf3IxAKZj1/2Y8QJeqfAmp78qkeGw8UBNWYykKprwzGF7++QNMXaAWbNXIeWkDb 35+Iyytzp820FzFM5Jpjw5TkX/BKpC2428/CfYsWuRVwhRApgNcq2ZWF4yLhlDBDrlDn xeVA== X-Gm-Message-State: ACrzQf1owcO7/dJ8gaKzyk2jDdruhmDGHkwfKqQf/QQW9MvF4xUYApFJ iQ2NIffWI5RxWjRL3PQzZX2QWDXlbymeY2l8CGlupEy2l1BBOQ== X-Google-Smtp-Source: AMsMyM5TQobHLK41F5OfseWoU08dHB1dbZiAeR+iqOn/KlXup8Xr6vyeCYAfCPjN7uGyCQdD6NsWLVHKMn1cjEOc60c= X-Received: by 2002:a81:7b56:0:b0:36b:5188:439d with SMTP id w83-20020a817b56000000b0036b5188439dmr8547890ywc.181.1666604708650; Mon, 24 Oct 2022 02:45:08 -0700 (PDT) MIME-Version: 1.0 References: <20221014075445.7938-6-haochen.jiang@intel.com> <20221024090125.16371-1-haochen.jiang@intel.com> In-Reply-To: <20221024090125.16371-1-haochen.jiang@intel.com> From: Uros Bizjak Date: Mon, 24 Oct 2022 11:44:57 +0200 Message-ID: Subject: Re: [PATCH] Support Intel CMPccXADD To: Haochen Jiang Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Mon, Oct 24, 2022 at 11:01 AM Haochen Jiang wrote: > > Hi all, > > I just refined CMPccXADD patch to make the enum in order intrin file > aligned with how opcode does. > > Ok for trunk? > > BRs, > Haochen > > gcc/ChangeLog: > > * common/config/i386/cpuinfo.h (get_available_features): > Detect cmpccxadd. > * common/config/i386/i386-common.cc > (OPTION_MASK_ISA2_CMPCCXADD_SET, > OPTION_MASK_ISA2_CMPCCXADD_UNSET): New. > (ix86_handle_option): Handle -mcmpccxadd, unset cmpccxadd when avx2 > is disabled. > * common/config/i386/i386-cpuinfo.h (enum processor_features): > Add FEATURE_CMPCCXADD. > * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for > cmpccxadd. > * config.gcc: Add cmpccxaddintrin.h. > * config/i386/cpuid.h (bit_CMPCCXADD): New. > * config/i386/i386-builtin-types.def: > Add DEF_FUNCTION_TYPE(INT, PINT, INT, INT, INT) > and DEF_FUNCTION_TYPE(LONGLONG, PLONGLONG, LONGLONG, LONGLONG, INT). > * config/i386/i386-builtin.def (BDESC): Add new builtins. > * config/i386/i386-c.cc (ix86_target_macros_internal): Define > __CMPCCXADD__. > * config/i386/i386-expand.cc (ix86_expand_special_args_builtin): > Add new parameter to indicate constant position. > Handle INT_FTYPE_PINT_INT_INT_INT > and LONGLONG_FTYPE_PLONGLONG_LONGLONG_LONGLONG_INT. > * config/i386/i386-isa.def (CMPCCXADD): Add DEF_PTA(CMPCCXADD). > * config/i386/i386-options.cc (isa2_opts): Add -mcmpccxadd. > (ix86_valid_target_attribute_inner_p): Handle cmpccxadd. > * config/i386/i386.opt: Add option -mcmpccxadd. > * config/i386/sync.md (cmpccxadd_): New define insn. > * config/i386/x86gprintrin.h: Include cmpccxaddintrin.h. > * doc/extend.texi: Document cmpccxadd. > * doc/invoke.texi: Document -mcmpccxadd. > * doc/sourcebuild.texi: Document target cmpccxadd. > * config/i386/cmpccxaddintrin.h: New file. > > gcc/testsuite/ChangeLog: > > * g++.dg/other/i386-2.C: Add -mcmpccxadd. > * g++.dg/other/i386-3.C: Ditto. > * gcc.target/i386/avx-1.c: Add builtin define for enum. > * gcc.target/i386/funcspec-56.inc: Add new target attribute. > * gcc.target/i386/sse-13.c: Add builtin define for enum. > * gcc.target/i386/sse-23.c: Ditto. > * gcc.target/i386/x86gprintrin-1.c: Add -mcmpccxadd for 64 bit target. > * gcc.target/i386/x86gprintrin-2.c: Add -mcmpccxadd for 64 bit target. > Add builtin define for enum. > * gcc.target/i386/x86gprintrin-3.c: Add -mcmpccxadd for 64 bit target. > * gcc.target/i386/x86gprintrin-4.c: Add mcmpccxadd for 64 bit target. > * gcc.target/i386/x86gprintrin-5.c: Add mcpmccxadd for 64 bit target. > Add builtin define for enum. > * gcc.target/i386/cmpccxadd-1.c: New test. > * gcc.target/i386/cmpccxadd-2.c: New test. > --- > gcc/common/config/i386/cpuinfo.h | 2 + > gcc/common/config/i386/i386-common.cc | 15 ++ > gcc/common/config/i386/i386-cpuinfo.h | 1 + > gcc/common/config/i386/i386-isas.h | 1 + > gcc/config.gcc | 3 +- > gcc/config/i386/cmpccxaddintrin.h | 89 +++++++++++ > gcc/config/i386/cpuid.h | 1 + > gcc/config/i386/i386-builtin-types.def | 4 + > gcc/config/i386/i386-builtin.def | 4 + > gcc/config/i386/i386-c.cc | 2 + > gcc/config/i386/i386-expand.cc | 22 ++- > gcc/config/i386/i386-isa.def | 1 + > gcc/config/i386/i386-options.cc | 4 +- > gcc/config/i386/i386.opt | 5 + > gcc/config/i386/sync.md | 42 ++++++ > gcc/config/i386/x86gprintrin.h | 2 + > gcc/doc/extend.texi | 5 + > gcc/doc/invoke.texi | 10 +- > gcc/doc/sourcebuild.texi | 3 + > gcc/testsuite/g++.dg/other/i386-2.C | 2 +- > gcc/testsuite/g++.dg/other/i386-3.C | 2 +- > gcc/testsuite/gcc.target/i386/avx-1.c | 4 + > gcc/testsuite/gcc.target/i386/cmpccxadd-1.c | 61 ++++++++ > gcc/testsuite/gcc.target/i386/cmpccxadd-2.c | 138 ++++++++++++++++++ > gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + > gcc/testsuite/gcc.target/i386/sse-13.c | 6 +- > gcc/testsuite/gcc.target/i386/sse-23.c | 6 +- > .../gcc.target/i386/x86gprintrin-1.c | 2 +- > .../gcc.target/i386/x86gprintrin-2.c | 6 +- > .../gcc.target/i386/x86gprintrin-3.c | 2 +- > .../gcc.target/i386/x86gprintrin-4.c | 2 +- > .../gcc.target/i386/x86gprintrin-5.c | 6 +- > gcc/testsuite/lib/target-supports.exp | 10 ++ > 33 files changed, 450 insertions(+), 15 deletions(-) > create mode 100644 gcc/config/i386/cmpccxaddintrin.h > create mode 100644 gcc/testsuite/gcc.target/i386/cmpccxadd-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/cmpccxadd-2.c +;; CMPCCXADD + +(define_insn "@cmpccxadd__1" + [(set (match_operand:SWI48x 1 "register_operand" "+r") + (match_operand:SWI48x 0 "memory_operand" "+m")) + (set (match_dup 0) + (unspec_volatile:SWI48x + [(match_dup 0) + (match_dup 1) + (match_operand:SWI48x 2 "register_operand" "r") + (match_operand:SI 3 "const_0_to_15_operand" "n")] + UNSPECV_CMPCCXADD)) + (clobber (reg:CC FLAGS_REG))] + "TARGET_CMPCCXADD && TARGET_64BIT" +{ IMO, the above should be defined much like the existing cmpxchg pattern (see atomic_compare_and_swap_1 named pattern), where the memory operand is updated like the one in xadd pattern (atomic_fetch_add named pattern). The above "+r" is not needed when matched operands are used (see mentioned two patterns). Using this approach, the expander won't be needed as well, since reload will take care of the correct input/output operand matching. Uros.