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From: Uros Bizjak <ubizjak@gmail.com>
Date: Tue, 5 Jan 2021 11:30:13 +0100
Message-ID: <CAFULd4YrfBMvExMzCvm5P1=wxGLLq=084qntsk14wJkJhEq3EQ@mail.gmail.com>
Subject: Re: [PATCH]i386: Optimize pmovskb on zero_extend of subreg HI of the
 result [PR98461]
To: Hongtao Liu <crazylht@gmail.com>
Cc: Jakub Jelinek <jakub@redhat.com>, GCC Patches <gcc-patches@gcc.gnu.org>, 
 Kirill Yukhin <kirill.yukhin@gmail.com>
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On Tue, Jan 5, 2021 at 11:25 AM Hongtao Liu <crazylht@gmail.com> wrote:
>
> On Tue, Jan 5, 2021 at 3:20 PM Uros Bizjak <ubizjak@gmail.com> wrote:
> >
> > On Tue, Jan 5, 2021 at 8:04 AM Uros Bizjak <ubizjak@gmail.com> wrote:
> > > >
> > > > +(define_split
> > > > +  [(set (match_operand:SI 0 "register_operand")
> > > > +        (zero_extend:SI
> > > > +          (not:HI
> > > > +            (subreg:HI
> > > > +              (unspec:SI
> > > > +                [(match_operand:V16QI 1 "register_operand")]
> > > > +                UNSPEC_MOVMSK) 0))))]
> > > > +  "TARGET_SSE2"
> > > > +  [(set (match_dup 2)
> > > > +        (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK))
> > > > +   (set (match_dup 0)
> > > > +        (match_dup 3))]
> > >
> > > Just write:
> > >
> > > (set (match_dup 0)
> > >     (xor:SI (match_dup 2)(const_int 65535))
> >
>
> Yes, changed.
>
> > BTW: This could be a universal combine splitter to simplify
> >
> > unsigned int foo (unsigned short z)
> > {
> >     return (unsigned short)~z;
> > }
> >
> > Trying 7 -> 8:
> >    7: r87:HI=~r88:SI#0
> >      REG_DEAD r88:SI
> >    8: r86:SI=zero_extend(r87:HI)
> >      REG_DEAD r87:HI
> > Failed to match this instruction:
> > (set (reg:SI 86)
> >    (zero_extend:SI (not:HI (subreg:HI (reg:SI 88) 0))))
> >
> > But combine does not "split" to one insns.
>
> Yes, according to PSabi, the top half of the register is not
> necessarily 0, so if you add the splitter, it just changes from notl +
> movzwl to xor + movzwl, which doesn't look better?

Indeed.

The patch is OK.

Uros.