From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 72283 invoked by alias); 18 Feb 2019 12:56:25 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 72196 invoked by uid 89); 18 Feb 2019 12:56:24 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=Ditto X-HELO: mail-it1-f194.google.com Received: from mail-it1-f194.google.com (HELO mail-it1-f194.google.com) (209.85.166.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 12:56:22 +0000 Received: by mail-it1-f194.google.com with SMTP id l15so27895002iti.4 for ; Mon, 18 Feb 2019 04:56:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=S3ur9oq34ZRNpPycdWr9ZfnXhyGTnP0Tch/sHDIKYwQ=; b=bXsCq7zNtG+exniqXKrTbx2QVwtzi7+EIEDjc+2WLEZasBKyHcw7GeoTUrwrQSncpt Op5+iJ1DyvoPxsVXjawiuO0l6L7q4OW/GIxdcSv8Ubs3Zh6URNl1iexMl9IPylHwyII1 lj5wxhDQTVLjqUEfO3lE2rvLsMuIOgBWCNzjZLyK2D5NIImj17tBzXLBFwSpzXy8rPeN e67eQ6x2xvaglPQXuCyr5sR9nc9dT/pxRl4AhPuqUH35ifLL/0+sPiCdZnOjkS6O+It6 flkZxOIynynTjz0jc2sqIQNLuYLSCCTkUu/zs5Jt4kyY0R62nIVUdYdVIUFg4hCEvrpo pSrA== MIME-Version: 1.0 References: <20190216224032.4889-1-hjl.tools@gmail.com> <20190216224032.4889-37-hjl.tools@gmail.com> In-Reply-To: <20190216224032.4889-37-hjl.tools@gmail.com> From: Uros Bizjak Date: Mon, 18 Feb 2019 12:56:00 -0000 Message-ID: Subject: Re: [PATCH 36/41] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE To: "H.J. Lu" Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-SW-Source: 2019-02/txt/msg01448.txt.bz2 On Sat, Feb 16, 2019 at 11:46 PM H.J. Lu wrote: > > From: Uros Bizjak > > 2019-02-14 Uro=C5=A1 Bizjak > > PR target/89021 > * config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute. > * config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto. > (*vec_concatv2sf_sse): Ditto. > (*vec_concatv2si_sse4_1): Ditto. > (*vec_concatv2si): Ditto. > (*vec_concatv4si_0): Ditto. > (*vec_concatv2di_0): Ditto. It looks like I forgot to add sse2_cvtpi2pd, sse2_cvtpd2pi and sse2_cvttpd2= pi. Uros. > --- > gcc/config/i386/i386.md | 4 ++++ > gcc/config/i386/sse.md | 16 ++++++++++++++-- > 2 files changed, 18 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 04ec0eeaa57..4cbbd4cf685 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -3683,6 +3683,10 @@ > (const_string "avx512bw") > ] > (const_string "*"))) > + (set (attr "mmx_isa") > + (if_then_else (eq_attr "alternative" "5,6") > + (const_string "native") > + (const_string "*"))) > (set (attr "type") > (cond [(eq_attr "alternative" "0,1,2,4") > (const_string "multi") > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 97ec3795b82..4b415d255e0 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -7209,6 +7209,10 @@ > (const_string "mmxmov") > ] > (const_string "sselog"))) > + (set (attr "mmx_isa") > + (if_then_else (eq_attr "alternative" "7,8") > + (const_string "native") > + (const_string "*"))) > (set (attr "prefix_data16") > (if_then_else (eq_attr "alternative" "3,4") > (const_string "1") > @@ -7244,7 +7248,8 @@ > movss\t{%1, %0|%0, %1} > punpckldq\t{%2, %0|%0, %2} > movd\t{%1, %0|%0, %1}" > - [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov") > + [(set_attr "mmx_isa" "*,*,native,native") > + (set_attr "type" "sselog,ssemov,mmxcvt,mmxmov") > (set_attr "mode" "V4SF,SF,DI,DI")]) > > (define_insn "*vec_concatv4sf" > @@ -14520,6 +14525,10 @@ > punpckldq\t{%2, %0|%0, %2} > movd\t{%1, %0|%0, %1}" > [(set_attr "isa" "noavx,noavx,avx,avx512dq,noavx,noavx,avx,*,*,*") > + (set (attr "mmx_isa") > + (if_then_else (eq_attr "alternative" "8,9") > + (const_string "native") > + (const_string "*"))) > (set (attr "type") > (cond [(eq_attr "alternative" "7") > (const_string "ssemov") > @@ -14557,6 +14566,7 @@ > punpckldq\t{%2, %0|%0, %2} > movd\t{%1, %0|%0, %1}" > [(set_attr "isa" "sse2,sse2,*,*,*,*") > + (set_attr "mmx_isa" "*,*,*,*,native,native") > (set_attr "type" "sselog,ssemov,sselog,ssemov,mmxcvt,mmxmov") > (set_attr "mode" "TI,TI,V4SF,SF,DI,DI")]) > > @@ -14586,7 +14596,8 @@ > "@ > %vmovq\t{%1, %0|%0, %1} > movq2dq\t{%1, %0|%0, %1}" > - [(set_attr "type" "ssemov") > + [(set_attr "mmx_isa" "*,native") > + (set_attr "type" "ssemov") > (set_attr "prefix" "maybe_vex,orig") > (set_attr "mode" "TI")]) > > @@ -14661,6 +14672,7 @@ > %vmovq\t{%1, %0|%0, %1} > movq2dq\t{%1, %0|%0, %1}" > [(set_attr "isa" "x64,*,*") > + (set_attr "mmx_isa" "*,*,native") > (set_attr "type" "ssemov") > (set_attr "prefix_rex" "1,*,*") > (set_attr "prefix" "maybe_vex,maybe_vex,orig") > -- > 2.20.1 >