From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x834.google.com (mail-qt1-x834.google.com [IPv6:2607:f8b0:4864:20::834]) by sourceware.org (Postfix) with ESMTPS id 60BCC3858C51 for ; Tue, 17 May 2022 10:07:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 60BCC3858C51 Received: by mail-qt1-x834.google.com with SMTP id g3so12664380qtb.7 for ; Tue, 17 May 2022 03:07:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1m36HaZ0DgaTkKoOdZYHcdQ4hND/QdI9cudP8QSkGAA=; b=qtGhQSA1ZqhGqpwM+BKMJEUwvJPtx6ysUd/SvTR0r7KZLvVW/R/XXl7JhjsmSrgMIr tRWV5fLPH/VkHf7uhKZKq5H6611vs+dvLebGSZ3m2bEsMuzRKzfw8kE3KzKZmAhn5/ju k1Ly250mo/22MveSQ1/dlY62e+V1eqaIbp1p0k4JIOgVCyf/dqB5bxwaX+3G2G0eRbnp KQxY4BsxlnGr8fjMMhRgVmUL4Iw/pyOXrh3rDwEkBbFeaIBUDgX21f4Nd5mbqcugdtmQ hAMioOp04LgvMEVS08fG7j+I3xk9tu1YhmDPq/TekqZszLjIHo3shC4c6mF3fphDuBKj pC/A== X-Gm-Message-State: AOAM533S8guCy0NZie2KIvLxjZ5iMLiUVSO6nxxfN4Xj8VkiuMtV9Yrm qtRpLT6iqXL06YyJgkB3NlwLHI4RNJnXFXyFmtA= X-Google-Smtp-Source: ABdhPJxToXQvdPiTiGxjW5vmt87PD1WcF0oD2yY5JMMCNsn4twbs1xxKvy/0oVtogwZbUXBZWYiP1V7Uany7Cg9C0FQ= X-Received: by 2002:ac8:5909:0:b0:2f3:d35f:cb8e with SMTP id 9-20020ac85909000000b002f3d35fcb8emr19084712qty.569.1652782031420; Tue, 17 May 2022 03:07:11 -0700 (PDT) MIME-Version: 1.0 References: <20220517030625.21971-1-hongtao.liu@intel.com> In-Reply-To: <20220517030625.21971-1-hongtao.liu@intel.com> From: Uros Bizjak Date: Tue, 17 May 2022 12:07:00 +0200 Message-ID: Subject: Re: [PATCH] [i386] recognize bzhi pattern when there's zero_extendsidi. To: liuhongt Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 May 2022 10:07:14 -0000 On Tue, May 17, 2022 at 5:06 AM liuhongt wrote: > > backend has > > 16550(define_insn "*bmi2_bzhi_3_2" > 16551 [(set (match_operand:SWI48 0 "register_operand" "=r") > 16552 (and:SWI48 > 16553 (plus:SWI48 > 16554 (ashift:SWI48 (const_int 1) > 16555 (match_operand:QI 2 "register_operand" "r")) > 16556 (const_int -1)) > 16557 (match_operand:SWI48 1 "nonimmediate_operand" "rm"))) > 16558 (clobber (reg:CC FLAGS_REG))] > 16559 "TARGET_BMI2" > 16560 "bzhi\t{%2, %1, %0|%0, %1, %2}" > 16561 [(set_attr "type" "bitmanip") > 16562 (set_attr "prefix" "vex") > 16563 (set_attr "mode" "")]) > > But there's extra zero_extend in pattern match. > > 424Failed to match this instruction: > 425(parallel [ > 426 (set (reg:DI 90) > 427 (zero_extend:DI (and:SI (plus:SI (ashift:SI (const_int 1 [0x1]) > 428 (subreg:QI (reg:SI 98) 0)) > 429 (const_int -1 [0xffffffffffffffff])) > 430 (subreg:SI (reg:DI 95) 0)))) > 431 (clobber (reg:CC 17 flags)) > 432 ]) > > Add new define_insn for it. > > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.. > Ok for trunk? > > gcc/ChangeLog: > > PR target/104375 > * config/i386/i386.md (*bmi2_bzhi_zero_extendsidi_4): New > define_insn. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr104375.c: New test. OK with a nit below. Thanks, Uros. > --- > gcc/config/i386/i386.md | 16 ++++++++++++++++ > gcc/testsuite/gcc.target/i386/pr104375.c | 9 +++++++++ > 2 files changed, 25 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/i386/pr104375.c > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index f9c06ff302a..ec7bdd04947 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -16636,6 +16636,22 @@ (define_insn "*bmi2_bzhi_3_3" > (set_attr "prefix" "vex") > (set_attr "mode" "")]) > > +(define_insn "*bmi2_bzhi_zero_extendsidi_4" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (zero_extend:DI > + (and:SI > + (plus:SI > + (ashift:SI (const_int 1) > + (match_operand:QI 2 "register_operand" "r")) > + (const_int -1)) > + (match_operand:SI 1 "nonimmediate_operand" "rm")))) > + (clobber (reg:CC FLAGS_REG))] > + "TARGET_BMI2 && TARGET_64BIT" Please put TARGET_64BIT first here. > + "bzhi\t{%q2, %q1, %q0|%q0, %q1, %q2}" > + [(set_attr "type" "bitmanip") > + (set_attr "prefix" "vex") > + (set_attr "mode" "DI")]) > + > (define_insn "bmi2_pdep_3" > [(set (match_operand:SWI48 0 "register_operand" "=r") > (unspec:SWI48 [(match_operand:SWI48 1 "register_operand" "r") > diff --git a/gcc/testsuite/gcc.target/i386/pr104375.c b/gcc/testsuite/gcc.target/i386/pr104375.c > new file mode 100644 > index 00000000000..5c9f511da5c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr104375.c > @@ -0,0 +1,9 @@ > +#/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-mbmi2 -O2" } */ > +/* { dg-final { scan-assembler-times {(?n)shrx[\t ]+} 1 } } */ > +/* { dg-final { scan-assembler-times {(?n)bzhi[\t ]+} 1 } } */ > + > +unsigned long long bextr_u64(unsigned long long w, unsigned off, unsigned int len) > +{ > + return (w >> off) & ((1U << len) - 1U); > +} > -- > 2.18.1 >