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From: Uros Bizjak <ubizjak@gmail.com>
Date: Thu, 12 Aug 2021 21:21:31 +0200
Message-ID: <CAFULd4ZCRUmaq3BvzdMXUxDr0hNYNAx6uY3iqGo4qFjmDkLOBw@mail.gmail.com>
Subject: Re: [PATCH] Extend ldexp{s, d}f3 to vscalefs{s, d} when TARGET_AVX512F
 and TARGET_SSE_MATH.
To: Hongtao Liu <crazylht@gmail.com>
Cc: liuhongt <hongtao.liu@intel.com>, 
 "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
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On Thu, Aug 12, 2021 at 6:40 AM Hongtao Liu <crazylht@gmail.com> wrote:

> > > > Hi:
> > > >   AVX512F supported vscalefs{s,d} which is the same as ldexp except=
 the second operand should be floating point.
> > > >   Bootstrapped and regtested on x86_64-linux-gnu{-m32,}.
> > > >
> > > > gcc/ChangeLog:
> > > >
> > > >         PR target/98309
> > > >         * config/i386/i386.md (ldexp<mode>3): Extend to vscalefs[sd=
]
> > > >         when TARGET_AVX512F and TARGET_SSE_MATH.
> > > >
> > > > gcc/testsuite/ChangeLog:
> > > >
> > > >         PR target/98309
> > > >         * gcc.target/i386/pr98309-1.c: New test.
> > > >         * gcc.target/i386/pr98309-2.c: New test.
> > >
> > > OK.
> >
> > Actually, we should introduce a scalar version of avx512f_vmscalef, so
> > we can avoid all subreg conversions with the vector-merge (VM)
> > version, and will also allow memory in operand 2.
> >
> > Please test the attached incremental patch.
> >
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,} on CLX.
> tests is fine.

Thanks, committed with the following ChangeLog:

[i386] Introduce scalar version of avx512f_vmscalef.

2021-08-12  Uro=C5=A1 Bizjak  <ubizjak@gmail.com>

gcc/
    PR target/98309
    * config/i386/i386.md (avx512f_scalef<mode>2): New insn pattern.
    (ldexp<mode>3): Use avx512f_scalef<mode>2.
    (UNSPEC_SCALEF): Move from ...
    * config/i386/sse.md (UNSPEC_SCALEF): ... here.

Uros.