From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qv1-xf2f.google.com (mail-qv1-xf2f.google.com [IPv6:2607:f8b0:4864:20::f2f]) by sourceware.org (Postfix) with ESMTPS id 5BA79385843E for ; Fri, 15 Apr 2022 07:54:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5BA79385843E Received: by mail-qv1-xf2f.google.com with SMTP id kl29so6064941qvb.2 for ; Fri, 15 Apr 2022 00:54:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rLH0I47Yv2qqLWsrwpIAjq2tjjtfccZ/9Lj3BfR/cs0=; b=BP4eAvTYXm7NAJfP5S/L7UfXCDK69aQExR2k5JeQFPHUB9GDsbyVeL/SkEcxbCGela S+VsomOYIrFSnTZnhjpT1KJBb7keg6uaA9OZ0kCohcyOjEdkZX43SzhmUR8yjbdWsupl jEyHIpwjTDWmW4bGPDODAs9Qd3Np4Trr2vNAxy9T7XMhz1DW8bBS3gChK9e2Wl08G1yg DGs9YDLwvY7m/P9BuKbDU5U9nqeL6PWdGWM1ihaM3I+yG0NnGQSnYhTMcooSk7hOfHNH QOcLlZruDPhFurzk8GAMuxLenRQC012jPfk2xBmre27dNOlSydFii4VNXDJyP/RzocQf yPJw== X-Gm-Message-State: AOAM532t/D1EBdsvtJLhzhTPuLbt3/AwW6+GKbK3hMhDBDnqV51Ewylv MN4P7MC3O3qWNk9KdwT8ZZFLfhhxvZ68z56vdcc= X-Google-Smtp-Source: ABdhPJxpi2l34B7FQ1KIy7H6hPsEwEJWvaNrNrVOqlnRjrOZWtkyb7KHhWL+FcewiBxmxvh74OlgNCJ9ncHcfkyml30= X-Received: by 2002:ad4:5dca:0:b0:441:6063:e235 with SMTP id m10-20020ad45dca000000b004416063e235mr6612197qvh.48.1650009255619; Fri, 15 Apr 2022 00:54:15 -0700 (PDT) MIME-Version: 1.0 References: <20220415042942.77387-1-hongyu.wang@intel.com> In-Reply-To: <20220415042942.77387-1-hongyu.wang@intel.com> From: Uros Bizjak Date: Fri, 15 Apr 2022 09:54:04 +0200 Message-ID: Subject: Re: [PATCH] i386: Correct target attribute for crc32 intrinsics To: Hongyu Wang Cc: "gcc-patches@gcc.gnu.org" , Hongtao Liu , "H. J. Lu" Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-7.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Apr 2022 07:54:18 -0000 On Fri, Apr 15, 2022 at 6:30 AM Hongyu Wang wrote: > > Hi, > > Complile _mm_crc32_u8/16/32/64 intrinsics with -mcrc32 > would meet target specific option mismatch. Correct target pragma > to fix. > > Bootstrapped/regtest on x86_64-pc-linux-gnu{-m32,}. > > Ok for master and backport to GCC 11? > > gcc/ChangeLog: > > * config/i386/smmintrin.h: Correct target pragma from sse4.1 > and sse4.2 to crc32 for crc32 intrinsics. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/crc32-6.c: Adjust to call builtin. > * gcc.target/i386/crc32-7.c: New test. > --- > gcc/config/i386/smmintrin.h | 25 +++++------------- > gcc/testsuite/gcc.target/i386/crc32-6.c | 2 +- > gcc/testsuite/gcc.target/i386/crc32-7.c | 34 +++++++++++++++++++++++++ > 3 files changed, 42 insertions(+), 19 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/crc32-7.c > > diff --git a/gcc/config/i386/smmintrin.h b/gcc/config/i386/smmintrin.h > index b42b212300f..eb6a451c10a 100644 > --- a/gcc/config/i386/smmintrin.h > +++ b/gcc/config/i386/smmintrin.h > @@ -810,17 +810,11 @@ _mm_cmpgt_epi64 (__m128i __X, __m128i __Y) > > #include > > -#ifndef __SSE4_1__ > +#ifndef __CRC32__ > #pragma GCC push_options > -#pragma GCC target("sse4.1") > -#define __DISABLE_SSE4_1__ > -#endif /* __SSE4_1__ */ > - > -#ifndef __SSE4_2__ > -#pragma GCC push_options > -#pragma GCC target("sse4.2") > -#define __DISABLE_SSE4_2__ > -#endif /* __SSE4_1__ */ > +#pragma GCC target("crc32") > +#define __DISABLE_CRC32__ > +#endif /* __CRC32__ */ > > /* Accumulate CRC32 (polynomial 0x11EDC6F41) value. */ > extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) > @@ -849,14 +843,9 @@ _mm_crc32_u64 (unsigned long long __C, unsigned long long __V) > } > #endif > > -#ifdef __DISABLE_SSE4_2__ > -#undef __DISABLE_SSE4_2__ > +#ifdef __DISABLE_CRC32__ > +#undef __DISABLE_CRC32__ > #pragma GCC pop_options > -#endif /* __DISABLE_SSE4_2__ */ > - > -#ifdef __DISABLE_SSE4_1__ > -#undef __DISABLE_SSE4_1__ > -#pragma GCC pop_options > -#endif /* __DISABLE_SSE4_1__ */ > +#endif /* __DISABLE_CRC32__ */ > > #endif /* _SMMINTRIN_H_INCLUDED */ > diff --git a/gcc/testsuite/gcc.target/i386/crc32-6.c b/gcc/testsuite/gcc.target/i386/crc32-6.c > index 464e3444069..1f306534bb8 100644 > --- a/gcc/testsuite/gcc.target/i386/crc32-6.c > +++ b/gcc/testsuite/gcc.target/i386/crc32-6.c > @@ -7,7 +7,7 @@ > unsigned int > test_mm_crc32_u8 (unsigned int CRC, unsigned char V) > { > - return _mm_crc32_u8 (CRC, V); > + return __builtin_ia32_crc32qi (CRC, V); This test should not be changed, it correctly reports ISA mismatch. It even passes -mno-crc32. Uros. > } > > /* { dg-error "needs isa option -mcrc32" "" { target *-*-* } 0 } */ > diff --git a/gcc/testsuite/gcc.target/i386/crc32-7.c b/gcc/testsuite/gcc.target/i386/crc32-7.c > new file mode 100644 > index 00000000000..2e310e38b82 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/crc32-7.c > @@ -0,0 +1,34 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mcrc32" } */ > +/* { dg-final { scan-assembler "crc32b\[^\\n\]*eax" } } */ > +/* { dg-final { scan-assembler "crc32w\[^\\n\]*eax" } } */ > +/* { dg-final { scan-assembler "crc32l\[^\\n\]*eax" } } */ > +/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target { ! ia32 } } } } */ > + > +#include > + > +unsigned int > +test_mm_crc32_u8 (unsigned int CRC, unsigned char V) > +{ > + return _mm_crc32_u8 (CRC, V); > +} > + > +unsigned int > +test_mm_crc32_u16 (unsigned int CRC, unsigned short V) > +{ > + return _mm_crc32_u16 (CRC, V); > +} > + > +unsigned int > +test_mm_crc32_u32 (unsigned int CRC, unsigned int V) > +{ > + return _mm_crc32_u32 (CRC, V); > +} > + > +#ifdef __x86_64__ > +unsigned long long > +test_mm_crc32_u64 (unsigned long long CRC, unsigned long long V) > +{ > + return _mm_crc32_u64 (CRC, V); > +} > +#endif > -- > 2.18.1 >