* [PATCH] i386: Add uavg_ceil patterns for 4-byte vectors [PR100637]
@ 2021-05-27 7:45 Uros Bizjak
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From: Uros Bizjak @ 2021-05-27 7:45 UTC (permalink / raw)
To: gcc-patches
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2021-05-27 Uroš Bizjak <ubizjak@gmail.com>
gcc/
PR target/100637
* config/i386/mmx.md (uavgv4qi3_ceil): New insn pattern.
(uavgv2hi3_ceil): Ditto.
gcc/testsuite/
PR target/100637
* gcc.target/i386/pr100637-3b.c (avgu): New test.
* gcc.target/i386/pr100637-3w.c (avgu): Ditto.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Pushed to master.
Uros.
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diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 453e8ea406d..23d88a4c265 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3270,6 +3270,47 @@ (define_expand "uavg<mode>3_ceil"
ix86_fixup_binary_operands_no_copy (PLUS, <MODE>mode, operands);
})
+(define_insn "uavgv4qi3_ceil"
+ [(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
+ (truncate:V4QI
+ (lshiftrt:V4HI
+ (plus:V4HI
+ (plus:V4HI
+ (zero_extend:V4HI
+ (match_operand:V4QI 1 "register_operand" "%0,Yw"))
+ (zero_extend:V4HI
+ (match_operand:V4QI 2 "register_operand" "x,Yw")))
+ (const_vector:V4HI [(const_int 1) (const_int 1)
+ (const_int 1) (const_int 1)]))
+ (const_int 1))))]
+ "TARGET_SSE2"
+ "@
+ pavgb\t{%2, %0|%0, %2}
+ vpavgb\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "mode" "TI")])
+
+(define_insn "uavgv2hi3_ceil"
+ [(set (match_operand:V2HI 0 "register_operand" "=x,Yw")
+ (truncate:V2HI
+ (lshiftrt:V2SI
+ (plus:V2SI
+ (plus:V2SI
+ (zero_extend:V2SI
+ (match_operand:V2HI 1 "register_operand" "%0,Yw"))
+ (zero_extend:V2SI
+ (match_operand:V2HI 2 "register_operand" "x,Yw")))
+ (const_vector:V2SI [(const_int 1) (const_int 1)]))
+ (const_int 1))))]
+ "TARGET_SSE2"
+ "@
+ pavgw\t{%2, %0|%0, %2}
+ vpavgw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sseiadd")
+ (set_attr "mode" "TI")])
+
(define_insn "mmx_psadbw"
[(set (match_operand:V1DI 0 "register_operand" "=y,x,Yw")
(unspec:V1DI [(match_operand:V8QI 1 "register_operand" "0,0,Yw")
diff --git a/gcc/testsuite/gcc.target/i386/pr100637-3b.c b/gcc/testsuite/gcc.target/i386/pr100637-3b.c
index 16df70059a9..b17f8b8c19b 100644
--- a/gcc/testsuite/gcc.target/i386/pr100637-3b.c
+++ b/gcc/testsuite/gcc.target/i386/pr100637-3b.c
@@ -54,3 +54,13 @@ void _abs (void)
}
/* { dg-final { scan-assembler "pabsb" } } */
+
+void avgu (void)
+{
+ int i;
+
+ for (i = 0; i < 4; i++)
+ ur[i] = (ua[i] + ub[i] + 1) >> 1;
+}
+
+/* { dg-final { scan-assembler "pavgb" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr100637-3w.c b/gcc/testsuite/gcc.target/i386/pr100637-3w.c
index 7f1882e7a56..b951f30f571 100644
--- a/gcc/testsuite/gcc.target/i386/pr100637-3w.c
+++ b/gcc/testsuite/gcc.target/i386/pr100637-3w.c
@@ -84,3 +84,13 @@ void _abs (void)
}
/* { dg-final { scan-assembler "pabsw" } } */
+
+void avgu (void)
+{
+ int i;
+
+ for (i = 0; i < 2; i++)
+ ur[i] = (ua[i] + ub[i] + 1) >> 1;
+}
+
+/* { dg-final { scan-assembler "pavgw" } } */
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