From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 107004 invoked by alias); 19 Dec 2018 08:23:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 106994 invoked by uid 89); 19 Dec 2018 08:23:33 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-it1-f196.google.com Received: from mail-it1-f196.google.com (HELO mail-it1-f196.google.com) (209.85.166.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 19 Dec 2018 08:23:31 +0000 Received: by mail-it1-f196.google.com with SMTP id b5so8195643iti.2 for ; Wed, 19 Dec 2018 00:23:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=qbyz/iHCWpxWAraja9V41ah+r0umImfS+MOqiNX72Ws=; b=nzkQ5huHaRHwhGKUPGncGweWPZ7EfPb9PPSvAYxW+bNS/7l8nBToZNB976uErGwiUX XNmK6msO1OB6Ggx7W6gQFMikPyuaXW+PpWX3sk/BIE0aPjLQIsHbN40yugk1OsVNieHu AcloqenlLRksFp8bArwjWZdqSZWU2anqgTh7aFC41pTgq09YhfB1/TNh2Zpm2ZLzXuqp PlRgIzq6BWL0iH3qaVEdxhyLD4ZBojBPIIog0UFftXrQbVum2zW3Mw3ikCD93/8xPAto 7pITp8Iv4vdFk7fnZWQdNToKb/4lvnGjdKYKHup4y5XN0ikaTc/rRwcwvT9GQ7nrTkfo aNuw== MIME-Version: 1.0 References: <20181218205328.GU23305@tucnak> In-Reply-To: <20181218205328.GU23305@tucnak> From: Uros Bizjak Date: Wed, 19 Dec 2018 08:23:00 -0000 Message-ID: Subject: Re: [PATCH] Allow _mm256_clmulepi64_epi128 even for just -mvcplmulqdq -mavx (PR target/88541) To: Jakub Jelinek Cc: "gcc-patches@gcc.gnu.org" Content-Type: text/plain; charset="UTF-8" X-SW-Source: 2018-12/txt/msg01366.txt.bz2 On Tue, Dec 18, 2018 at 9:53 PM Jakub Jelinek wrote: > > Hi! > > As mentioned in the PR, there is a VEX encoded vpclmulqdq instruction > with ymm arguments that needs VPCLMULQDQ ISA, and then EVEX encoded > vpclmulqdq with zmm arguments that needs VPCLMULQDQ + AVX512F ISAs and > vpclmulqdq with xmm or ymm arguments that needs VPCLMULQDQ + AVX512VL ISAs. > > So, _mm256_clmulepi64_epi128 can be done just with AVX (so that VEX encoded > instructions are handled) + VPCLMULQDQ ISAs. > The corresponding builtin matches this: > BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX, CODE_FOR_vpclmulqdq_v4di, "__builtin_ia32_vpclmulqdq_v4di", IX86_BUILTIN_VPCLMULQDQ4, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT) > > Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for > trunk? > > 2018-12-18 Jakub Jelinek > > PR target/88541 > * config/i386/vpclmulqdqintrin.h (_mm256_clmulepi64_epi128): Enable > for -mavx -mvpclmulqdq rather than just for -mavx512vl -mvpclmulqdq. > > * gcc.target/i386/avx-vpclmulqdq-1.c: New test. OK. Thanks, Uros. > --- gcc/config/i386/vpclmulqdqintrin.h.jj 2018-06-13 10:05:54.775128332 +0200 > +++ gcc/config/i386/vpclmulqdqintrin.h 2018-12-18 20:09:37.693666571 +0100 > @@ -53,9 +53,9 @@ _mm512_clmulepi64_epi128 (__m512i __A, _ > #pragma GCC pop_options > #endif /* __DISABLE_VPCLMULQDQF__ */ > > -#if !defined(__VPCLMULQDQ__) || !defined(__AVX512VL__) > +#if !defined(__VPCLMULQDQ__) || !defined(__AVX__) > #pragma GCC push_options > -#pragma GCC target("vpclmulqdq,avx512vl") > +#pragma GCC target("vpclmulqdq,avx") > #define __DISABLE_VPCLMULQDQ__ > #endif /* __VPCLMULQDQ__ */ > > @@ -78,6 +78,4 @@ _mm256_clmulepi64_epi128 (__m256i __A, _ > #pragma GCC pop_options > #endif /* __DISABLE_VPCLMULQDQ__ */ > > - > #endif /* _VPCLMULQDQINTRIN_H_INCLUDED */ > - > --- gcc/testsuite/gcc.target/i386/avx-vpclmulqdq-1.c.jj 2018-12-18 20:13:28.683960294 +0100 > +++ gcc/testsuite/gcc.target/i386/avx-vpclmulqdq-1.c 2018-12-18 20:12:41.140723131 +0100 > @@ -0,0 +1,10 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mavx -mvpclmulqdq" } */ > + > +#include > + > +__m256i > +foo (__m256i x, __m256i y) > +{ > + return _mm256_clmulepi64_epi128 (x, y, 0); > +} > > Jakub