From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x82a.google.com (mail-qt1-x82a.google.com [IPv6:2607:f8b0:4864:20::82a]) by sourceware.org (Postfix) with ESMTPS id 40C723858C54 for ; Mon, 6 Jun 2022 10:25:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 40C723858C54 Received: by mail-qt1-x82a.google.com with SMTP id t21so2989656qtw.11 for ; Mon, 06 Jun 2022 03:25:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=HKuV3xJtrof/LO7x46gXF1F0DQJmR0rS3qN6BSLLkeA=; b=rG3B7q4HTVhTBAL4jT23w2nEuuvpXsMdmU4wHYoeE/OMHU272gczWckmGH1kGMg841 f79de935Au5fTzlI/htQ5KhGeKzIhlTRrKkGTvYiNUmBD5tJVeQu7eQ6dSu5ZiMwcew8 iwXq9vTySA57h/i1P3vpavT1Z2dH9talFZUH2oFuniDtj4LZ+Jly4D3B7JzwtzFY0Dlh ltLB6M+23RLuQDaMMG9hfwZekM4OxaUJqSoB8dhtiLPUR87ldidA4FBNu1eaDMln+rlI Zymsip/UhzTNn+FuCSKuL5A5B7kpOs17GysNmDJDd96nGkkqLX/hTisN3C4FTtmWz/1V WxDw== X-Gm-Message-State: AOAM531FUSwFgRTbExC93tOErp6iBik/nonGMv+nvEIWcxi6V1rOXNsW AiIGV6rY/20m3Y48lZAPXOWZoJWYR1vpQo4bKFA= X-Google-Smtp-Source: ABdhPJwMYtzBoklzdh1uD0sHLcX08MdYLClf1iFY3iOtRXLYwpFeIT6r1zlj3VSPMu81oa7OxYadRTzHC1mY78/4H6Y= X-Received: by 2002:ac8:574d:0:b0:2f3:b4aa:700f with SMTP id 13-20020ac8574d000000b002f3b4aa700fmr17376863qtx.54.1654511136523; Mon, 06 Jun 2022 03:25:36 -0700 (PDT) MIME-Version: 1.0 References: <016e01d87900$615a7a30$240f6e90$@nextmovesoftware.com> In-Reply-To: <016e01d87900$615a7a30$240f6e90$@nextmovesoftware.com> From: Uros Bizjak Date: Mon, 6 Jun 2022 12:25:25 +0200 Message-ID: Subject: Re: [x86 PATCH] Double word implementation of and; cmp to not; test optimization. To: Roger Sayle Cc: GCC Patches Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jun 2022 10:25:40 -0000 On Sun, Jun 5, 2022 at 7:19 PM Roger Sayle wrote: > > > This patch extends the recent and;cmp to not;test optimization to also > perform this transformation for TImode on TARGET_64BIT and DImode on -m32, > One motivation for this is that it's a step to fixing the current failure > of gcc.target/i386/pr65105-5.c on -m32. > > A more direct benefit for x86_64 is that the following code: > > int foo(__int128 x, __int128 y) > { > return (x & y) == y; > } > > improves (with -O2 -mbmi) from: > > movq %rdi, %r8 > movq %rsi, %rdi > movq %rdx, %rsi > andq %rcx, %rdi > movq %r8, %rax > andq %rdx, %rax > movq %rdi, %rdx > xorq %rsi, %rax > xorq %rcx, %rdx > orq %rdx, %rax > sete %al > movzbl %al, %eax > ret > > to the much better: > > movq %rdi, %r8 > movq %rsi, %rdi > andn %rdx, %r8, %rax > andn %rcx, %rdi, %rsi > orq %rsi, %rax > sete %al > movzbl %al, %eax > ret > > The major theme of this patch is to generalize many of i386.md's > *di3_doubleword patterns to become *_doubleword patterns, i.e. > whenever there exists a "double word" optimization for DImode with -m32, > there should be an equivalent TImode optimization on TARGET_64BIT. > > The following patch has been tested on x86_64-pc-linux-gnu with > make bootstrap and make -k check, where on TARGET_64BIT there are > no new failures, but paradoxically with --target_board=unix{-m32} > the other dg-final clause in gcc.target/i386/pr65105-5.c now fails. > Counter-intuitively, this is progress, and pr65105-5.c may now be > fixed (without using peephole2) simply by tweaking the STV pass to > handle andn/test (in a follow-up patch). > OK for mainline? > > > 2022-06-05 Roger Sayle > > gcc/ChangeLog > * config/i386/i386.cc (ix86_rtx_costs) : Provide costs > for double word comparisons and tests (comparisons against zero). > * config/i386/i386.md (*test_not_doubleword): Split DWI > and;cmp into andn;cmp $0 as a pre-reload splitter. > (define_expand and3): Generalize from SWIM1248x to SWIDWI. > (define_insn_and_split "*anddi3_doubleword"): Rename/generalize... > (define_insn_and_split "*and3_doubleword"): ... to this. > (define_insn "*andndi3_doubleword"): Rename and generalize... > (define_insn "*andn3_doubleword): ... to this. > (define_split): Split andn when TARGET_BMI for both modes. > (define_split): Split andn when !TARGET_BMI for both modes. > (define_expand 3): Generalize from SWIM1248x to > SWIDWI. > (define_insn_and_split "*3_doubleword): Generalize > from DI mode to both modes. > > gcc/testsuite/ChangeLog > * gcc.target/i386/testnot-3.c: New test case. -(define_insn_and_split "*anddi3_doubleword" - [(set (match_operand:DI 0 "nonimmediate_operand") - (and:DI - (match_operand:DI 1 "nonimmediate_operand") - (match_operand:DI 2 "x86_64_szext_general_operand"))) +(define_insn_and_split "*and3_doubleword" + [(set (match_operand: 0 "nonimmediate_operand") + (and: + (match_operand: 1 "nonimmediate_operand") + (match_operand: 2 ""))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT - && ix86_binary_operator_ok (AND, DImode, operands) + "ix86_binary_operator_ok (AND, mode, operands) && ix86_pre_reload_split ()" "#" "&& 1" - [(const_int 0)] + [(parallel + [(set (match_dup 0) (and:DWIH (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (parallel + [(set (match_dup 3) (and:DWIH (match_dup 4) (match_dup 5))) + (clobber (reg:CC FLAGS_REG))])] Please also note that the above pattern generation will never be reached, you have unconditional DONE in the insn preparation statement. { - split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]); + split_double_mode (mode, &operands[0], 3, &operands[0], &operands[3]); if (operands[2] == const0_rtx) emit_move_insn (operands[0], const0_rtx); else if (operands[2] == constm1_rtx) emit_move_insn (operands[0], operands[1]); else - emit_insn (gen_andsi3 (operands[0], operands[1], operands[2])); + ix86_expand_binary_operator (AND, mode, &operands[0]); if (operands[5] == const0_rtx) emit_move_insn (operands[3], const0_rtx); else if (operands[5] == constm1_rtx) emit_move_insn (operands[3], operands[4]); else - emit_insn (gen_andsi3 (operands[3], operands[4], operands[5])); + ix86_expand_binary_operator (AND, mode, &operands[3]); DONE; }) -(define_insn_and_split "*di3_doubleword" - [(set (match_operand:DI 0 "nonimmediate_operand") - (any_or:DI - (match_operand:DI 1 "nonimmediate_operand") - (match_operand:DI 2 "x86_64_szext_general_operand"))) +(define_insn_and_split "*3_doubleword" + [(set (match_operand: 0 "nonimmediate_operand") + (any_or: + (match_operand: 1 "nonimmediate_operand") + (match_operand: 2 ""))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT - && ix86_binary_operator_ok (, DImode, operands) + "ix86_binary_operator_ok (, mode, operands) && ix86_pre_reload_split ()" "#" "&& 1" - [(const_int 0)] + [(parallel + [(set (match_dup 0) (any_or:DWIH (match_dup 1) (match_dup 2))) + (clobber (reg:CC FLAGS_REG))]) + (parallel + [(set (match_dup 3) (any_or:DWIH (match_dup 4) (match_dup 5))) + (clobber (reg:CC FLAGS_REG))])] Also here. Uros.