From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by sourceware.org (Postfix) with ESMTPS id 0F4B13858CD1 for ; Wed, 22 May 2024 08:35:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 0F4B13858CD1 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 0F4B13858CD1 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::22a ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716366943; cv=none; b=XIwD2XnGAw/kf8rWc8awFB8Qab78flasc1i3IGgqHIGiIrxiAYXkKulytDXgGzWbdUpw4uExOKBRoRtKGNSsEjMEZcDcuFJ5n6LcPRE8+bwEeDd3A5JfTzyqXNnjxQ9gzrZ+m8QHdZGTDS5sMe/thD4HGaCXO4ZlhfuskewCrWc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1716366943; c=relaxed/simple; bh=JScffD8n8awCXdK3pl8dc0Qk2NpD/6d36+fcKjyV6JM=; h=DKIM-Signature:MIME-Version:From:Date:Message-ID:Subject:To; b=Gw45cSKAMl+rT+YMS6NmdDGx4i5KUauzEsrgYzuU7L+BMqOiaOCCuZ+LHlS5r2N2uBvbErRMq1mzuu6JfzRyLmWbK46Rvd2qFOrVhu6zb+ansXT437lmAq0lKd0qD1YL29PMh9sm7BoXX3NyiOfZi5BCw7sPPUMd1El7J3ufV5s= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2e1fa824504so58332751fa.0 for ; Wed, 22 May 2024 01:35:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1716366937; x=1716971737; darn=gcc.gnu.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Fxq9XDmUWBmCx3lC07ZzcXybHh1OGSdAdsRWFk28mvc=; b=Sy2J0aKdNcUSOSWAuJq7/iX41yxTufEz8tVfTZAzGzN3j83hM15R3aWKxiL36CY61y +moOzza3RDFy2ebgY4/rE06bOroReU8JyaKkgGSHJwXe13brlOEsc7OK9DTeGfvXptUJ loMJ0SYQ3vsAZ7rZq4IHyzjDFQPlIvg6QQ2zBbix5YqP+X7bbOR0KDAydYSCzlnqNIKy Hgrjd2CN8D3M9tEID4zXXTvXE3Rp+7cdHAYNp4Efp/qhTkUeqO+N/Xj0nzicZAbj3P6l l856ygHdjetMnECUHNniqguIq+xH9/nz0JHdif3OHkMSZiN3dZ7Hyli3nv3Zdhzpm5pB yhUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1716366937; x=1716971737; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fxq9XDmUWBmCx3lC07ZzcXybHh1OGSdAdsRWFk28mvc=; b=qGHBLkUjNtJVyV2w6EqXDW6u1nLFdr+pARV784GACnrPRVm+kr+mMjYwKFqOE865ZR 81l8Uzjt3oBpTX9hsNMNe+RUvUkcW6PbC9fikTeepXhqGZGlyrCn65jfEG9wY/L3dm/W F6uBO4I53JqyM8U2hCl+I1NeaTmFCaFvciJCmn3f9v9Iecb+tLfAkM9zOwQ8Z9OVm8Ne cyZlpFkA30bbXHwHy1PK9PzVqUYnzzE0tT2nToMZqehhq+2FbvkBS9iEhOwsdfmHmLdN 4UYK+W2XXJvJdVrKG/zJpnnClv/NRvXWm28FSF9Wf+uPLXBXRcMwxAfiaUUGqq/MPRu8 OQLw== X-Gm-Message-State: AOJu0YwfCvRIrEOec9mmC7/ZvCFkqU4w14kgy3WM0kGu+MseWbFvYr6I PaJleIeftHNo/Z4LbRb0fAqC5UaE+hwec0PsXgxuWSfzti99CLuHPeeci0lbYzjTodswSYr35+I c8hY92QyOlbra7o/g8uCtCatIEiY= X-Google-Smtp-Source: AGHT+IEieZHf6w6R984c4t5w9zLDADYhZxFXspHcldOv/eJqKN+c4RnFn8h2bW0Ma4XPHdhAVktCcHCbtuNg9K4inDw= X-Received: by 2002:a2e:b049:0:b0:2e0:aeba:ba90 with SMTP id 38308e7fff4ca-2e949563a1cmr7600751fa.46.1716366936822; Wed, 22 May 2024 01:35:36 -0700 (PDT) MIME-Version: 1.0 References: <20240515070226.3760873-1-lingling.kong@intel.com> In-Reply-To: From: Uros Bizjak Date: Wed, 22 May 2024 10:35:25 +0200 Message-ID: Subject: Re: [PATCH v2 1/8] [APX NF]: Support APX NF add To: "Kong, Lingling" Cc: "gcc-patches@gcc.gnu.org" , "Liu, Hongtao" , "Wang, Hongyu" Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Wed, May 22, 2024 at 10:29=E2=80=AFAM Kong, Lingling wrote: > > > I wonder if we can use "define_subst" to conditionally add flags clobbe= r > > for !TARGET_APX_NF targets. Even the example for "Define Subst" uses th= e insn > > w/ and w/o the clobber, so I think it is worth considering this approac= h. > > > > Uros. > > Good Suggestion, I defined new subst for no flags, and Bootstrapped and r= egtested on x86_64-linux-gnu. Also supported SPEC 2017 run normally on Inte= l software development emulator. > Ok for trunk? > > Thanks, > Lingling > > Subject: [PATCH v2 1/8] [APX NF]: Support APX NF add > APX NF(no flags) feature implements suppresses the update of status flags > for arithmetic operations. > > For NF add, it is not clear whether nf add can be faster than lea. If so, > the pattern needs to be adjusted to perfer lea generation. > > gcc/ChangeLog: > > * config/i386/i386-opts.h (enum apx_features): Add nf > enumeration. > * config/i386/i386.h (TARGET_APX_NF): New. > * config/i386/i386.md (nf_subst): New define_subst. > (nf_name): New subst_attr. > (nf_prefix): Ditto. > (nf_condition): Ditto. > (nf_mem_constraint): Ditto. > (nf_applied): Ditto. > (*add_1_nf): New define_insn. > (addhi_1_nf): Ditto. > (addqi_1_nf): Ditto. > * config/i386/i386.opt: Add apx_nf enumeration. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/apx-ndd.c: Fixed test. > * gcc.target/i386/apx-nf.c: New test. LGTM, but I'll leave the final approval to Hongtao. Thanks, Uros. > > Co-authored-by: Lingling Kong > --- > gcc/config/i386/i386-opts.h | 3 +- > gcc/config/i386/i386.h | 1 + > gcc/config/i386/i386.md | 179 +++++++++++++++--------- > gcc/config/i386/i386.opt | 3 + > gcc/testsuite/gcc.target/i386/apx-ndd.c | 2 +- > gcc/testsuite/gcc.target/i386/apx-nf.c | 6 + > 6 files changed, 126 insertions(+), 68 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/apx-nf.c > > diff --git a/gcc/config/i386/i386-opts.h b/gcc/config/i386/i386-opts.h > index ef2825803b3..60176ce609f 100644 > --- a/gcc/config/i386/i386-opts.h > +++ b/gcc/config/i386/i386-opts.h > @@ -140,7 +140,8 @@ enum apx_features { > apx_push2pop2 =3D 1 << 1, > apx_ndd =3D 1 << 2, > apx_ppx =3D 1 << 3, > - apx_all =3D apx_egpr | apx_push2pop2 | apx_ndd | apx_ppx, > + apx_nf =3D 1<< 4, > + apx_all =3D apx_egpr | apx_push2pop2 | apx_ndd | apx_ppx | apx_nf, > }; > > #endif > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h > index 529edff93a4..f20ae4726da 100644 > --- a/gcc/config/i386/i386.h > +++ b/gcc/config/i386/i386.h > @@ -55,6 +55,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively= . If not, see > #define TARGET_APX_PUSH2POP2 (ix86_apx_features & apx_push2pop2) > #define TARGET_APX_NDD (ix86_apx_features & apx_ndd) > #define TARGET_APX_PPX (ix86_apx_features & apx_ppx) > +#define TARGET_APX_NF (ix86_apx_features & apx_nf) > > #include "config/vxworks-dummy.h" > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 764bfe20ff2..bae344518bd 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -6233,28 +6233,6 @@ > } > }) > > > -;; Load effective address instructions > - > -(define_insn "*lea" > - [(set (match_operand:SWI48 0 "register_operand" "=3Dr") > - (match_operand:SWI48 1 "address_no_seg_operand" "Ts"))] > - "ix86_hardreg_mov_ok (operands[0], operands[1])" > -{ > - if (SImode_address_operand (operands[1], VOIDmode)) > - { > - gcc_assert (TARGET_64BIT); > - return "lea{l}\t{%E1, %k0|%k0, %E1}"; > - } > - else > - return "lea{}\t{%E1, %0|%0, %E1}"; > -} > - [(set_attr "type" "lea") > - (set (attr "mode") > - (if_then_else > - (match_operand 1 "SImode_address_operand") > - (const_string "SI") > - (const_string "")))]) > - > (define_peephole2 > [(set (match_operand:SWI48 0 "register_operand") > (match_operand:SWI48 1 "address_no_seg_operand"))] > @@ -6290,6 +6268,13 @@ > [(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup = 1))) > (clobber (reg:CC FLAGS_REG))])] > "operands[1] =3D GEN_INT (exact_log2 (INTVAL (operands[1])));") > + > +(define_split > + [(set (match_operand:SWI48 0 "general_reg_operand") > + (mult:SWI48 (match_dup 0) (match_operand:SWI48 1 "const1248_opera= nd")))] > + "TARGET_APX_NF && reload_completed" > + [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 1)))] > + "operands[1] =3D GEN_INT (exact_log2 (INTVAL (operands[1])));") > > > ;; Add instructions > > @@ -6437,48 +6422,65 @@ > (clobber (reg:CC FLAGS_REG))])] > "split_double_mode (mode, &operands[0], 1, &operands[0], &operands= [5]);") > > -(define_insn "*add_1" > - [(set (match_operand:SWI48 0 "nonimmediate_operand" "=3Drm,r,r,r,r,r,r= ") > +(define_subst_attr "nf_name" "nf_subst" "_nf" "") > +(define_subst_attr "nf_prefix" "nf_subst" "%{nf%} " "") > +(define_subst_attr "nf_condition" "nf_subst" "TARGET_APX_NF" "true") > +(define_subst_attr "nf_mem_constraint" "nf_subst" "je" "m") > +(define_subst_attr "nf_applied" "nf_subst" "true" "false") > + > +(define_subst "nf_subst" > + [(set (match_operand:SWI 0) > + (match_operand:SWI 1))] > + "" > + [(set (match_dup 0) > + (match_dup 1)) > + (clobber (reg:CC FLAGS_REG))]) > + > +(define_insn "*add_1" > + [(set (match_operand:SWI48 0 "nonimmediate_operand" "=3Drm,r,r,r,r,r,r,r") > (plus:SWI48 > - (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r,rje,jM,= r") > - (match_operand:SWI48 2 "x86_64_general_operand" "re,BM,0,le,r,e= ,BM"))) > - (clobber (reg:CC FLAGS_REG))] > - "ix86_binary_operator_ok (PLUS, mode, operands, TARGET_APX_NDD)" > + (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,0,r,r,rje,j= M,r") > + (match_operand:SWI48 2 "x86_64_general_operand" "r,e,BM,0,le,r,= e,BM")))] > + "ix86_binary_operator_ok (PLUS, mode, operands, TARGET_APX_NDD) > + && " > { > bool use_ndd =3D get_attr_isa (insn) =3D=3D ISA_APX_NDD; > switch (get_attr_type (insn)) > { > case TYPE_LEA: > - return "#"; > + if (TARGET_APX_NDD && ) > + return "%{nf%} add{}\t{%2, %1, %0|%0, %1, %2}"; > + else > + return "#"; > > case TYPE_INCDEC: > if (operands[2] =3D=3D const1_rtx) > - return use_ndd ? "inc{}\t{%1, %0|%0, %1}" > - : "inc{}\t%0"; > + return use_ndd ? "inc{}\t{%1, %0|%0, %1}= " > + : "inc{}\t%0"; > else > { > gcc_assert (operands[2] =3D=3D constm1_rtx); > - return use_ndd ? "dec{}\t{%1, %0|%0, %1}" > - : "dec{}\t%0"; > + return use_ndd ? "dec{}\t{%1, %0|%0, %1= }" > + : "dec{}\t%0"; > } > > default: > /* For most processors, ADD is faster than LEA. This alternative > was added to use ADD as much as possible. */ > - if (which_alternative =3D=3D 2) > + if (which_alternative =3D=3D 3) > std::swap (operands[1], operands[2]); > > if (x86_maybe_negate_const_int (&operands[2], mode)) > - return use_ndd ? "sub{}\t{%2, %1, %0|%0, %1, %2}" > - : "sub{}\t{%2, %0|%0, %2}"; > + return use_ndd ? "sub{}\t{%2, %1, %0|%0,= %1, %2}" > + : "sub{}\t{%2, %0|%0, %2}"; > > - return use_ndd ? "add{}\t{%2, %1, %0|%0, %1, %2}" > - : "add{}\t{%2, %0|%0, %2}"; > + return use_ndd ? "add{}\t{%2, %1, %0|%0, %= 1, %2}" > + : "add{}\t{%2, %0|%0, %2}"; > } > } > - [(set_attr "isa" "*,*,*,*,apx_ndd,apx_ndd,apx_ndd") > + [(set_attr "isa" "*,*,*,*,*,apx_ndd,apx_ndd,apx_ndd") > (set (attr "type") > - (cond [(eq_attr "alternative" "3") > + (cond [(eq_attr "alternative" "4") > (const_string "lea") > (match_operand:SWI48 2 "incdec_operand") > (const_string "incdec") > @@ -6491,6 +6493,28 @@ > (const_string "*"))) > (set_attr "mode" "")]) > > +;; Load effective address instructions > + > +(define_insn "*lea" > + [(set (match_operand:SWI48 0 "register_operand" "=3Dr") > + (match_operand:SWI48 1 "address_no_seg_operand" "Ts"))] > + "ix86_hardreg_mov_ok (operands[0], operands[1])" > +{ > + if (SImode_address_operand (operands[1], VOIDmode)) > + { > + gcc_assert (TARGET_64BIT); > + return "lea{l}\t{%E1, %k0|%k0, %E1}"; > + } > + else > + return "lea{}\t{%E1, %0|%0, %E1}"; > +} > + [(set_attr "type" "lea") > + (set (attr "mode") > + (if_then_else > + (match_operand 1 "SImode_address_operand") > + (const_string "SI") > + (const_string "")))]) > + > ;; It may seem that nonimmediate operand is proper one for operand 1. > ;; The addsi_1 pattern allows nonimmediate operand at that place and > ;; we take care in ix86_binary_operator_ok to not allow two memory > @@ -6552,26 +6576,29 @@ > (const_string "*"))) > (set_attr "mode" "SI")]) > > -(define_insn "*addhi_1" > +(define_insn "*addhi_1" > [(set (match_operand:HI 0 "nonimmediate_operand" "=3Drm,r,r,Yp,r,r") > (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r,Yp,rm= ,r") > - (match_operand:HI 2 "general_operand" "rn,m,0,ln,rn,m"))= ) > - (clobber (reg:CC FLAGS_REG))] > - "ix86_binary_operator_ok (PLUS, HImode, operands, TARGET_APX_NDD)" > + (match_operand:HI 2 "general_operand" "rn,m,0,ln,rn,m"))= )] > + "ix86_binary_operator_ok (PLUS, HImode, operands, TARGET_APX_NDD) > + && " > { > bool use_ndd =3D get_attr_isa (insn) =3D=3D ISA_APX_NDD; > switch (get_attr_type (insn)) > { > case TYPE_LEA: > - return "#"; > + if (TARGET_APX_NDD && ) > + return "%{nf%} add{w}\t{%2, %1, %0|%0, %1, %2}"; > + else > + return "#"; > > case TYPE_INCDEC: > if (operands[2] =3D=3D const1_rtx) > - return use_ndd ? "inc{w}\t{%1, %0|%0, %1}" : "inc{w}\t%0"; > + return use_ndd ? "inc{w}\t{%1, %0|%0, %1}" : "inc{w}\t%0"; > else > { > gcc_assert (operands[2] =3D=3D constm1_rtx); > - return use_ndd ? "dec{w}\t{%1, %0|%0, %1}" : "dec{w}\t%0"; > + return use_ndd ? "dec{w}\t{%1, %0|%0, %1}" : "dec{w}\t%0"; > } > > default: > @@ -6581,11 +6608,11 @@ > std::swap (operands[1], operands[2]); > > if (x86_maybe_negate_const_int (&operands[2], HImode)) > - return use_ndd ? "sub{w}\t{%2, %1, %0|%0, %1, %2}" > - : "sub{w}\t{%2, %0|%0, %2}"; > + return use_ndd ? "sub{w}\t{%2, %1, %0|%0, %1, %2}" > + : "sub{w}\t{%2, %0|%0, %2}"; > > - return use_ndd ? "add{w}\t{%2, %1, %0|%0, %1, %2}" > - : "add{w}\t{%2, %0|%0, %2}"; > + return use_ndd ? "add{w}\t{%2, %1, %0|%0, %1, %2}" > + : "add{w}\t{%2, %0|%0, %2}"; > } > } > [(set_attr "isa" "*,*,*,*,apx_ndd,apx_ndd") > @@ -6603,33 +6630,36 @@ > (const_string "*"))) > (set_attr "mode" "HI,HI,HI,SI,HI,HI")]) > > -(define_insn "*addqi_1" > +(define_insn "*addqi_1" > [(set (match_operand:QI 0 "nonimmediate_operand" "=3Dqm,q,q,r,r,Yp,r,r= ") > (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,q,0,r,Y= p,rm,r") > - (match_operand:QI 2 "general_operand" "qn,m,0,rn,0,ln,rn= ,m"))) > - (clobber (reg:CC FLAGS_REG))] > - "ix86_binary_operator_ok (PLUS, QImode, operands, TARGET_APX_NDD)" > + (match_operand:QI 2 "general_operand" "qn,m,0,rn,0,ln,rn= ,m")))] > + "ix86_binary_operator_ok (PLUS, QImode, operands, TARGET_APX_NDD) > + && " > { > bool widen =3D (get_attr_mode (insn) !=3D MODE_QI); > bool use_ndd =3D get_attr_isa (insn) =3D=3D ISA_APX_NDD; > switch (get_attr_type (insn)) > { > case TYPE_LEA: > - return "#"; > + if (TARGET_APX_NDD && ) > + return "%{nf%} add{b}\t{%2, %1, %0|%0, %1, %2}"; > + else > + return "#"; > > case TYPE_INCDEC: > if (operands[2] =3D=3D const1_rtx) > if (use_ndd) > - return "inc{b}\t{%1, %0|%0, %1}"; > + return "inc{b}\t{%1, %0|%0, %1}"; > else > - return widen ? "inc{l}\t%k0" : "inc{b}\t%0"; > + return widen ? "inc{l}\t%k0" : "inc{b}\t%= 0"; > else > { > gcc_assert (operands[2] =3D=3D constm1_rtx); > if (use_ndd) > - return "dec{b}\t{%1, %0|%0, %1}"; > + return "dec{b}\t{%1, %0|%0, %1}"; > else > - return widen ? "dec{l}\t%k0" : "dec{b}\t%0"; > + return widen ? "dec{l}\t%k0" : "dec{b}\= t%0"; > } > > default: > @@ -6641,16 +6671,16 @@ > if (x86_maybe_negate_const_int (&operands[2], QImode)) > { > if (use_ndd) > - return "sub{b}\t{%2, %1, %0|%0, %1, %2}"; > + return "sub{b}\t{%2, %1, %0|%0, %1, %2}"; > else > - return widen ? "sub{l}\t{%2, %k0|%k0, %2}" > - : "sub{b}\t{%2, %0|%0, %2}"; > + return widen ? "sub{l}\t{%2, %k0|%k0, %2}" > + : "sub{b}\t{%2, %0|%0, %2}"; > } > if (use_ndd) > - return "add{b}\t{%2, %1, %0|%0, %1, %2}"; > + return "add{b}\t{%2, %1, %0|%0, %1, %2}"; > else > - return widen ? "add{l}\t{%k2, %k0|%k0, %k2}" > - : "add{b}\t{%2, %0|%0, %2}"; > + return widen ? "add{l}\t{%k2, %k0|%k0, %k2}" > + : "add{b}\t{%2, %0|%0, %2}"; > } > } > [(set_attr "isa" "*,*,*,*,*,*,apx_ndd,apx_ndd") > @@ -6824,6 +6854,23 @@ > } > }) > > +(define_split > + [(set (match_operand:SWI 0 "register_operand") > + (plus:SWI (match_operand:SWI 1 "register_operand") > + (match_operand:SWI 2 "")))] > + "TARGET_APX_NF && reload_completed > + && ix86_lea_for_add_ok (insn, operands)" > + [(set (match_dup 0) > + (plus: (match_dup 1) (match_dup 2)))] > +{ > + if (mode !=3D mode) > + { > + operands[0] =3D gen_lowpart (mode, operands[0]); > + operands[1] =3D gen_lowpart (mode, operands[1]); > + operands[2] =3D gen_lowpart (mode, operands[2]); > + } > +}) > + > ;; Convert add to the lea pattern to avoid flags dependency. > (define_split > [(set (match_operand:DI 0 "register_operand") > diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt > index d5f793a9e8b..66021d59d4e 100644 > --- a/gcc/config/i386/i386.opt > +++ b/gcc/config/i386/i386.opt > @@ -1356,6 +1356,9 @@ Enum(apx_features) String(ndd) Value(apx_ndd) Set(4= ) > EnumValue > Enum(apx_features) String(ppx) Value(apx_ppx) Set(5) > > +EnumValue > +Enum(apx_features) String(nf) Value(apx_nf) Set(6) > + > EnumValue > Enum(apx_features) String(all) Value(apx_all) Set(1) > > diff --git a/gcc/testsuite/gcc.target/i386/apx-ndd.c b/gcc/testsuite/gcc.= target/i386/apx-ndd.c > index 0eb751ad225..0ff4df0780c 100644 > --- a/gcc/testsuite/gcc.target/i386/apx-ndd.c > +++ b/gcc/testsuite/gcc.target/i386/apx-ndd.c > @@ -1,5 +1,5 @@ > /* { dg-do compile { target { ! ia32 } } } */ > -/* { dg-options "-mapxf -march=3Dx86-64 -O2" } */ > +/* { dg-options "-mapx-features=3Degpr,push2pop2,ndd,ppx -march=3Dx86-64= -O2" } */ > /* { dg-final { scan-assembler-not "movl"} } */ > > #include > diff --git a/gcc/testsuite/gcc.target/i386/apx-nf.c b/gcc/testsuite/gcc.t= arget/i386/apx-nf.c > new file mode 100644 > index 00000000000..3adc7a27902 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/apx-nf.c > @@ -0,0 +1,6 @@ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-mapx-features=3Degpr,push2pop2,ndd,ppx,nf -march=3Dx86= -64 -O2" } */ > +/* { dg-final { scan-assembler-times "\{nf\} add" 4 } } */ > + > +#include "apx-ndd.c" > + > -- > 2.31.1 > >