* [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl.
@ 2015-08-04 11:47 Kirill Yukhin
2015-08-04 12:10 ` Uros Bizjak
0 siblings, 1 reply; 7+ messages in thread
From: Kirill Yukhin @ 2015-08-04 11:47 UTC (permalink / raw)
To: GCC Patches; +Cc: Uros Bizjak
Hello,
For vec_dup and vec_concat patterns (of v2df mode) second operand
is of scalar mode, so `ix86_hard_regno_mode_ok’ didn’t block EVEX registers,
of non-512b modes (when AVX-512VL is turned off).
This turns into 128/256b xmm[>15] regs emit on -march=knl.
There’re should be more patterns w/ similar issue. Will look for them later.
Bootstrapped and regtested.
If no objections, I'll commit it tomorrow morning (Moscow time).
gcc/
* config/i386/i386.md (define_attr "isa"): Addd avx512vl and
noavx512vl.
(define_attr "enabled"): Handle avx521vl and noavx512vl.
* config/i386/sse.md (define_insn "vec_dupv2df<mask_name>"): Split
AVX-512 alternative out of SSE.
(define_insn "*vec_concatv2df"): Ditto.
--
Thanks, K
commit 924990a6e8d38b6ebff9dd9a79e285ef81890202
Author: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Mon Aug 3 15:21:06 2015 +0300
Fix vec_concatv2df and vec_dupv2df to block wrongly enabled AVX-512VL insns.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 5c5c1fc..9ffe9aa 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -784,7 +784,8 @@
(define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
- fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq"
+ fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq,
+ avx512vl,noavx512vl"
(const_string "base"))
(define_attr "enabled" ""
@@ -819,6 +820,8 @@
(eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW")
(eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ")
(eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ")
+ (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
+ (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
]
(const_int 1)))
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0970f0e..a509369 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8638,44 +8638,47 @@
(set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
(define_insn "vec_dupv2df<mask_name>"
- [(set (match_operand:V2DF 0 "register_operand" "=x,v")
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
(vec_duplicate:V2DF
- (match_operand:DF 1 "nonimmediate_operand" " 0,vm")))]
+ (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))]
"TARGET_SSE2 && <mask_avx512vl_condition>"
"@
unpcklpd\t%0, %0
- %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
- [(set_attr "isa" "noavx,sse3")
+ %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}
+ vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ [(set_attr "isa" "noavx,sse3,avx512vl")
(set_attr "type" "sselog1")
- (set_attr "prefix" "orig,maybe_vex")
- (set_attr "mode" "V2DF,DF")])
+ (set_attr "prefix" "orig,maybe_vex,evex")
+ (set_attr "mode" "V2DF,DF,DF")])
(define_insn "*vec_concatv2df"
- [(set (match_operand:V2DF 0 "register_operand" "=x,v,v,x,x,v,x,x")
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x,v,x,x")
(vec_concat:V2DF
- (match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0")
- (match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))]
+ (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,m,0,0")
+ (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))]
"TARGET_SSE
&& (!(MEM_P (operands[1]) && MEM_P (operands[2]))
|| (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))"
"@
unpcklpd\t{%2, %0|%0, %2}
vunpcklpd\t{%2, %1, %0|%0, %1, %2}
+ vunpcklpd\t{%2, %1, %0|%0, %1, %2}
%vmovddup\t{%1, %0|%0, %1}
+ vmovddup\t{%1, %0|%0, %1}
movhpd\t{%2, %0|%0, %2}
vmovhpd\t{%2, %1, %0|%0, %1, %2}
%vmovsd\t{%1, %0|%0, %1}
movlhps\t{%2, %0|%0, %2}
movhps\t{%2, %0|%0, %2}"
- [(set_attr "isa" "sse2_noavx,avx,sse3,sse2_noavx,avx,sse2,noavx,noavx")
+ [(set_attr "isa" "sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx")
(set (attr "type")
(if_then_else
(eq_attr "alternative" "0,1,2")
(const_string "sselog")
(const_string "ssemov")))
- (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
- (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig")
- (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")])
+ (set_attr "prefix_data16" "*,*,*,*,*,1,*,*,*,*")
+ (set_attr "prefix" "orig,vex,evex,maybe_vex,evex,orig,vex,maybe_vex,orig,orig")
+ (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl.
2015-08-04 11:47 [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl Kirill Yukhin
@ 2015-08-04 12:10 ` Uros Bizjak
2015-08-04 12:31 ` Kirill Yukhin
0 siblings, 1 reply; 7+ messages in thread
From: Uros Bizjak @ 2015-08-04 12:10 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: GCC Patches
On Tue, Aug 4, 2015 at 1:47 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello,
>
> For vec_dup and vec_concat patterns (of v2df mode) second operand
> is of scalar mode, so `ix86_hard_regno_mode_ok’ didn’t block EVEX registers,
> of non-512b modes (when AVX-512VL is turned off).
> This turns into 128/256b xmm[>15] regs emit on -march=knl.
>
> There’re should be more patterns w/ similar issue. Will look for them later.
>
> Bootstrapped and regtested.
>
> If no objections, I'll commit it tomorrow morning (Moscow time).
>
> gcc/
> * config/i386/i386.md (define_attr "isa"): Addd avx512vl and
> noavx512vl.
> (define_attr "enabled"): Handle avx521vl and noavx512vl.
> * config/i386/sse.md (define_insn "vec_dupv2df<mask_name>"): Split
> AVX-512 alternative out of SSE.
> (define_insn "*vec_concatv2df"): Ditto.
>
> - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
> - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig")
> - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")])
> + (set_attr "prefix_data16" "*,*,*,*,*,1,*,*,*,*")
Please change the above to:
(set (attr "prefix_data16")
(if_then_else (eq_attr "alternative" "5")
(const_string "1")
(const_string "*")))
Uros.
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl.
2015-08-04 12:10 ` Uros Bizjak
@ 2015-08-04 12:31 ` Kirill Yukhin
2015-08-04 12:34 ` Kirill Yukhin
0 siblings, 1 reply; 7+ messages in thread
From: Kirill Yukhin @ 2015-08-04 12:31 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On 04 Aug 14:10, Uros Bizjak wrote:
> On Tue, Aug 4, 2015 at 1:47 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> > Hello,
> > - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
> > - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig")
> > - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")])
> > + (set_attr "prefix_data16" "*,*,*,*,*,1,*,*,*,*")
>
> Please change the above to:
>
> (set (attr "prefix_data16")
> (if_then_else (eq_attr "alternative" "5")
> (const_string "1")
> (const_string "*")))
Thanks, fixed!
>
> Uros.
commit 20df38ce6fed082155b9860b0a1c5511894fdd84
Author: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Tue Aug 4 10:36:10 2015 +0300
Merge SSE 4.1 and AVX ptest patterns. Extend iterator for new one.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 128c5af..f93a5ce 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31734,9 +31734,9 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
{ OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
- { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
+ { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
/* SSE4.2 */
{ OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
@@ -31892,9 +31892,9 @@ static const struct builtin_description bdesc_args[] =
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
- { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
+ { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0970f0e..0ffc27d 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -299,6 +299,12 @@
V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
;; All DImode vector integer modes
+(define_mode_iterator V_AVX
+ [V16QI V8HI V4SI V2DI V4SF V2DF
+ (V32QI "TARGET_AVX") (V16HI "TARGET_AVX")
+ (V8SI "TARGET_AVX") (V4DI "TARGET_AVX")
+ (V8SF "TARGET_AVX") (V4DF"TARGET_AVX")])
+
(define_mode_iterator VI8
[(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX") V2DI])
@@ -566,7 +572,11 @@
(define_mode_attr sse4_1
[(V4SF "sse4_1") (V2DF "sse4_1")
(V8SF "avx") (V4DF "avx")
- (V8DF "avx512f")])
+ (V8DF "avx512f")
+ (V4DI "avx") (V2DI "sse4_1")
+ (V8SI "avx") (V4SI "sse4_1")
+ (V16QI "sse4_1") (V32QI "avx")
+ (V8HI "sse4_1") (V16HI "avx")])
(define_mode_attr avxsizesuffix
[(V64QI "512") (V32HI "512") (V16SI "512") (V8DI "512")
@@ -14640,30 +14650,23 @@
;; ptest is very similar to comiss and ucomiss when setting FLAGS_REG.
;; But it is not a really compare instruction.
-(define_insn "avx_ptest256"
- [(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:V4DI 0 "register_operand" "x")
- (match_operand:V4DI 1 "nonimmediate_operand" "xm")]
- UNSPEC_PTEST))]
- "TARGET_AVX"
- "vptest\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
- (set_attr "prefix_extra" "1")
- (set_attr "prefix" "vex")
- (set_attr "btver2_decode" "vector")
- (set_attr "mode" "OI")])
-
-(define_insn "sse4_1_ptest"
+(define_insn "<sse4_1>_ptest<mode>"
[(set (reg:CC FLAGS_REG)
- (unspec:CC [(match_operand:V2DI 0 "register_operand" "Yr,*x")
- (match_operand:V2DI 1 "nonimmediate_operand" "Yrm,*xm")]
+ (unspec:CC [(match_operand:V_AVX 0 "register_operand" "Yr, *x, x")
+ (match_operand:V_AVX 1 "nonimmediate_operand" "Yrm, *xm, xm")]
UNSPEC_PTEST))]
"TARGET_SSE4_1"
"%vptest\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecomi")
+ [(set_attr "isa" "*,*,avx")
+ (set_attr "type" "ssecomi")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
- (set_attr "mode" "TI")])
+ (set (attr "btver2_decode")
+ (if_then_else
+ (match_test "<sseinsnmode>mode==OImode")
+ (const_string "vector")
+ (const_string "*")))
+ (set_attr "mode" "<sseinsnmode>")])
(define_insn "<sse4_1>_round<ssemodesuffix><avxsizesuffix>"
[(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x")
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl.
2015-08-04 12:31 ` Kirill Yukhin
@ 2015-08-04 12:34 ` Kirill Yukhin
2015-08-05 8:07 ` Kirill Yukhin
0 siblings, 1 reply; 7+ messages in thread
From: Kirill Yukhin @ 2015-08-04 12:34 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches
On 04 Aug 15:31, Kirill Yukhin wrote:
> On 04 Aug 14:10, Uros Bizjak wrote:
> > On Tue, Aug 4, 2015 at 1:47 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> > > Hello,
> > > - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
> > > - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig")
> > > - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")])
> > > + (set_attr "prefix_data16" "*,*,*,*,*,1,*,*,*,*")
> >
> > Please change the above to:
> >
> > (set (attr "prefix_data16")
> > (if_then_else (eq_attr "alternative" "5")
> > (const_string "1")
> > (const_string "*")))
> Thanks, fixed!
> >
> > Uros.
Wrong patch. Here is proper.
commit 1055739cb51648794a01afd85f59efadd14378ed
Author: Kirill Yukhin <kirill.yukhin@intel.com>
Date: Mon Aug 3 15:21:06 2015 +0300
Fix vec_concatv2df and vec_dupv2df to block wrongly enabled AVX-512VL insns.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 5c5c1fc..9ffe9aa 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -784,7 +784,8 @@
(define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
- fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq"
+ fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq,
+ avx512vl,noavx512vl"
(const_string "base"))
(define_attr "enabled" ""
@@ -819,6 +820,8 @@
(eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW")
(eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ")
(eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ")
+ (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
+ (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
]
(const_int 1)))
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 0970f0e..ca1ec2e 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8638,44 +8638,50 @@
(set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
(define_insn "vec_dupv2df<mask_name>"
- [(set (match_operand:V2DF 0 "register_operand" "=x,v")
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
(vec_duplicate:V2DF
- (match_operand:DF 1 "nonimmediate_operand" " 0,vm")))]
+ (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))]
"TARGET_SSE2 && <mask_avx512vl_condition>"
"@
unpcklpd\t%0, %0
- %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
- [(set_attr "isa" "noavx,sse3")
+ %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}
+ vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ [(set_attr "isa" "noavx,sse3,avx512vl")
(set_attr "type" "sselog1")
- (set_attr "prefix" "orig,maybe_vex")
- (set_attr "mode" "V2DF,DF")])
+ (set_attr "prefix" "orig,maybe_vex,evex")
+ (set_attr "mode" "V2DF,DF,DF")])
(define_insn "*vec_concatv2df"
- [(set (match_operand:V2DF 0 "register_operand" "=x,v,v,x,x,v,x,x")
+ [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x,v,x,x")
(vec_concat:V2DF
- (match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0")
- (match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))]
+ (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,m,0,0")
+ (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))]
"TARGET_SSE
&& (!(MEM_P (operands[1]) && MEM_P (operands[2]))
|| (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))"
"@
unpcklpd\t{%2, %0|%0, %2}
vunpcklpd\t{%2, %1, %0|%0, %1, %2}
+ vunpcklpd\t{%2, %1, %0|%0, %1, %2}
%vmovddup\t{%1, %0|%0, %1}
+ vmovddup\t{%1, %0|%0, %1}
movhpd\t{%2, %0|%0, %2}
vmovhpd\t{%2, %1, %0|%0, %1, %2}
%vmovsd\t{%1, %0|%0, %1}
movlhps\t{%2, %0|%0, %2}
movhps\t{%2, %0|%0, %2}"
- [(set_attr "isa" "sse2_noavx,avx,sse3,sse2_noavx,avx,sse2,noavx,noavx")
+ [(set_attr "isa" "sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx")
(set (attr "type")
(if_then_else
(eq_attr "alternative" "0,1,2")
(const_string "sselog")
(const_string "ssemov")))
- (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
- (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig")
- (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")])
+ (set (attr "prefix_data16")
+ (if_then_else (eq_attr "alternative" "5")
+ (const_string "1")
+ (const_string "*")))
+ (set_attr "prefix" "orig,vex,evex,maybe_vex,evex,orig,vex,maybe_vex,orig,orig")
+ (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")])
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl.
2015-08-04 12:34 ` Kirill Yukhin
@ 2015-08-05 8:07 ` Kirill Yukhin
2015-08-06 7:27 ` Uros Bizjak
0 siblings, 1 reply; 7+ messages in thread
From: Kirill Yukhin @ 2015-08-05 8:07 UTC (permalink / raw)
To: Uros Bizjak, Jakub Jelinek, Richard Biener, Jeff Law; +Cc: GCC Patches
Hello,
Is it ok to backport the patch to gcc-5-branch?
--
Thanks, K
> On 04 Aug 15:31, Kirill Yukhin wrote:
>
> commit 1055739cb51648794a01afd85f59efadd14378ed
> Author: Kirill Yukhin <kirill.yukhin@intel.com>
> Date: Mon Aug 3 15:21:06 2015 +0300
>
> Fix vec_concatv2df and vec_dupv2df to block wrongly enabled AVX-512VL insns.
>
> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
> index 5c5c1fc..9ffe9aa 100644
> --- a/gcc/config/i386/i386.md
> +++ b/gcc/config/i386/i386.md
> @@ -784,7 +784,8 @@
> (define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
> sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
> avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
> - fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq"
> + fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq,
> + avx512vl,noavx512vl"
> (const_string "base"))
>
> (define_attr "enabled" ""
> @@ -819,6 +820,8 @@
> (eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW")
> (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ")
> (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ")
> + (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
> + (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
> ]
> (const_int 1)))
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 0970f0e..ca1ec2e 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -8638,44 +8638,50 @@
> (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
>
> (define_insn "vec_dupv2df<mask_name>"
> - [(set (match_operand:V2DF 0 "register_operand" "=x,v")
> + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
> (vec_duplicate:V2DF
> - (match_operand:DF 1 "nonimmediate_operand" " 0,vm")))]
> + (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))]
> "TARGET_SSE2 && <mask_avx512vl_condition>"
> "@
> unpcklpd\t%0, %0
> - %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
> - [(set_attr "isa" "noavx,sse3")
> + %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}
> + vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
> + [(set_attr "isa" "noavx,sse3,avx512vl")
> (set_attr "type" "sselog1")
> - (set_attr "prefix" "orig,maybe_vex")
> - (set_attr "mode" "V2DF,DF")])
> + (set_attr "prefix" "orig,maybe_vex,evex")
> + (set_attr "mode" "V2DF,DF,DF")])
>
> (define_insn "*vec_concatv2df"
> - [(set (match_operand:V2DF 0 "register_operand" "=x,v,v,x,x,v,x,x")
> + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x,v,x,x")
> (vec_concat:V2DF
> - (match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0")
> - (match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))]
> + (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,m,0,0")
> + (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))]
> "TARGET_SSE
> && (!(MEM_P (operands[1]) && MEM_P (operands[2]))
> || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))"
> "@
> unpcklpd\t{%2, %0|%0, %2}
> vunpcklpd\t{%2, %1, %0|%0, %1, %2}
> + vunpcklpd\t{%2, %1, %0|%0, %1, %2}
> %vmovddup\t{%1, %0|%0, %1}
> + vmovddup\t{%1, %0|%0, %1}
> movhpd\t{%2, %0|%0, %2}
> vmovhpd\t{%2, %1, %0|%0, %1, %2}
> %vmovsd\t{%1, %0|%0, %1}
> movlhps\t{%2, %0|%0, %2}
> movhps\t{%2, %0|%0, %2}"
> - [(set_attr "isa" "sse2_noavx,avx,sse3,sse2_noavx,avx,sse2,noavx,noavx")
> + [(set_attr "isa" "sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx")
> (set (attr "type")
> (if_then_else
> (eq_attr "alternative" "0,1,2")
> (const_string "sselog")
> (const_string "ssemov")))
> - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
> - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig")
> - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")])
> + (set (attr "prefix_data16")
> + (if_then_else (eq_attr "alternative" "5")
> + (const_string "1")
> + (const_string "*")))
> + (set_attr "prefix" "orig,vex,evex,maybe_vex,evex,orig,vex,maybe_vex,orig,orig")
> + (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")])
>
> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
> ;;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl.
2015-08-05 8:07 ` Kirill Yukhin
@ 2015-08-06 7:27 ` Uros Bizjak
2015-08-06 11:13 ` Uros Bizjak
0 siblings, 1 reply; 7+ messages in thread
From: Uros Bizjak @ 2015-08-06 7:27 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Jakub Jelinek, Richard Biener, Jeff Law, GCC Patches
On Wed, Aug 5, 2015 at 10:07 AM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello,
>
> Is it ok to backport the patch to gcc-5-branch?
A minor attribute fix is needed, please update type attribute of
*vec_concatv2df for added alternatives, also for mainline.
Otherwise, the patch looks safe, so OK for backport after a couple of days.
Thanks,
Uros.
> --
> Thanks, K
>
>> On 04 Aug 15:31, Kirill Yukhin wrote:
>>
>> commit 1055739cb51648794a01afd85f59efadd14378ed
>> Author: Kirill Yukhin <kirill.yukhin@intel.com>
>> Date: Mon Aug 3 15:21:06 2015 +0300
>>
>> Fix vec_concatv2df and vec_dupv2df to block wrongly enabled AVX-512VL insns.
>>
>> diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
>> index 5c5c1fc..9ffe9aa 100644
>> --- a/gcc/config/i386/i386.md
>> +++ b/gcc/config/i386/i386.md
>> @@ -784,7 +784,8 @@
>> (define_attr "isa" "base,x64,x64_sse4,x64_sse4_noavx,x64_avx,nox64,
>> sse2,sse2_noavx,sse3,sse4,sse4_noavx,avx,noavx,
>> avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
>> - fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq"
>> + fma_avx512f,avx512bw,noavx512bw,avx512dq,noavx512dq,
>> + avx512vl,noavx512vl"
>> (const_string "base"))
>>
>> (define_attr "enabled" ""
>> @@ -819,6 +820,8 @@
>> (eq_attr "isa" "noavx512bw") (symbol_ref "!TARGET_AVX512BW")
>> (eq_attr "isa" "avx512dq") (symbol_ref "TARGET_AVX512DQ")
>> (eq_attr "isa" "noavx512dq") (symbol_ref "!TARGET_AVX512DQ")
>> + (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
>> + (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
>> ]
>> (const_int 1)))
>>
>> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
>> index 0970f0e..ca1ec2e 100644
>> --- a/gcc/config/i386/sse.md
>> +++ b/gcc/config/i386/sse.md
>> @@ -8638,44 +8638,50 @@
>> (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")])
>>
>> (define_insn "vec_dupv2df<mask_name>"
>> - [(set (match_operand:V2DF 0 "register_operand" "=x,v")
>> + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v")
>> (vec_duplicate:V2DF
>> - (match_operand:DF 1 "nonimmediate_operand" " 0,vm")))]
>> + (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))]
>> "TARGET_SSE2 && <mask_avx512vl_condition>"
>> "@
>> unpcklpd\t%0, %0
>> - %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
>> - [(set_attr "isa" "noavx,sse3")
>> + %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}
>> + vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
>> + [(set_attr "isa" "noavx,sse3,avx512vl")
>> (set_attr "type" "sselog1")
>> - (set_attr "prefix" "orig,maybe_vex")
>> - (set_attr "mode" "V2DF,DF")])
>> + (set_attr "prefix" "orig,maybe_vex,evex")
>> + (set_attr "mode" "V2DF,DF,DF")])
>>
>> (define_insn "*vec_concatv2df"
>> - [(set (match_operand:V2DF 0 "register_operand" "=x,v,v,x,x,v,x,x")
>> + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,v,x,x,v,x,x")
>> (vec_concat:V2DF
>> - (match_operand:DF 1 "nonimmediate_operand" " 0,v,m,0,x,m,0,0")
>> - (match_operand:DF 2 "vector_move_operand" " x,v,1,m,m,C,x,m")))]
>> + (match_operand:DF 1 "nonimmediate_operand" " 0,x,v,m,m,0,x,m,0,0")
>> + (match_operand:DF 2 "vector_move_operand" " x,x,v,1,1,m,m,C,x,m")))]
>> "TARGET_SSE
>> && (!(MEM_P (operands[1]) && MEM_P (operands[2]))
>> || (TARGET_SSE3 && rtx_equal_p (operands[1], operands[2])))"
>> "@
>> unpcklpd\t{%2, %0|%0, %2}
>> vunpcklpd\t{%2, %1, %0|%0, %1, %2}
>> + vunpcklpd\t{%2, %1, %0|%0, %1, %2}
>> %vmovddup\t{%1, %0|%0, %1}
>> + vmovddup\t{%1, %0|%0, %1}
>> movhpd\t{%2, %0|%0, %2}
>> vmovhpd\t{%2, %1, %0|%0, %1, %2}
>> %vmovsd\t{%1, %0|%0, %1}
>> movlhps\t{%2, %0|%0, %2}
>> movhps\t{%2, %0|%0, %2}"
>> - [(set_attr "isa" "sse2_noavx,avx,sse3,sse2_noavx,avx,sse2,noavx,noavx")
>> + [(set_attr "isa" "sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx")
>> (set (attr "type")
>> (if_then_else
>> (eq_attr "alternative" "0,1,2")
>> (const_string "sselog")
>> (const_string "ssemov")))
>> - (set_attr "prefix_data16" "*,*,*,1,*,*,*,*")
>> - (set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex,orig,orig")
>> - (set_attr "mode" "V2DF,V2DF,DF,V1DF,V1DF,DF,V4SF,V2SF")])
>> + (set (attr "prefix_data16")
>> + (if_then_else (eq_attr "alternative" "5")
>> + (const_string "1")
>> + (const_string "*")))
>> + (set_attr "prefix" "orig,vex,evex,maybe_vex,evex,orig,vex,maybe_vex,orig,orig")
>> + (set_attr "mode" "V2DF,V2DF,V2DF, DF, DF, V1DF,V1DF,DF,V4SF,V2SF")])
>>
>> ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
>> ;;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl.
2015-08-06 7:27 ` Uros Bizjak
@ 2015-08-06 11:13 ` Uros Bizjak
0 siblings, 0 replies; 7+ messages in thread
From: Uros Bizjak @ 2015-08-06 11:13 UTC (permalink / raw)
To: Kirill Yukhin; +Cc: Jakub Jelinek, Richard Biener, Jeff Law, GCC Patches
On Thu, Aug 6, 2015 at 9:27 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
>> Is it ok to backport the patch to gcc-5-branch?
>
> A minor attribute fix is needed, please update type attribute of
> *vec_concatv2df for added alternatives, also for mainline.
Fixed in mainline with the following patch:
2015-08-06 Uros Bizjak <ubizjak@gmail.com>
* config/i386/sse.md (*vec_concatv2df): Declare added
alternatives as sselog type.
Bootstrapped and regression tested on x86_64-linux-gnu, committed to
mainline SVN.
Uros.
Index: sse.md
===================================================================
--- sse.md (revision 226670)
+++ sse.md (working copy)
@@ -8683,7 +8683,7 @@
[(set_attr "isa"
"sse2_noavx,avx,avx512vl,sse3,avx512vl,sse2_noavx,avx,sse2,noavx,noavx")
(set (attr "type")
(if_then_else
- (eq_attr "alternative" "0,1,2")
+ (eq_attr "alternative" "0,1,2,3,4")
(const_string "sselog")
(const_string "ssemov")))
(set (attr "prefix_data16")
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-08-06 11:13 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2015-08-04 11:47 [PATCH, i386] Disable AVX-512VL insns for scalar mode operands on -march=knl Kirill Yukhin
2015-08-04 12:10 ` Uros Bizjak
2015-08-04 12:31 ` Kirill Yukhin
2015-08-04 12:34 ` Kirill Yukhin
2015-08-05 8:07 ` Kirill Yukhin
2015-08-06 7:27 ` Uros Bizjak
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